www.ti.com

APPLICATION INFORMATION

1

2

3

4

8

7

6

5

TL7660

+

-

+

-

C

10 µF

1

C

10 µF

2

–V

OUT

V+

(5 V)

I

S

I

L

R

L

C

OSC

(see

Note A)

8

3

2

5

3

7

V

= –V

OUT

IN

S

2

S

1

S

3

S

4

C

2

V

IN

C

1

TL7660

CMOS VOLTAGE CONVERTER

SCAS794 – JUNE 2006

A.

In the circuit, there is no external capacitor applied to terminal 7. However when device is plugged into a test

socket,there is usually a very small but finite stray capacitance present on the order of 10 pF.

Figure 1. Test Circuit

The TL7660 contains all the necessary circuitry to complete a negative voltage converter, with the exception of

two external capacitors which may be inexpensive 10

µF polarized electrolytic types. The mode of operation of

the device may be best understood by considering Figure 2, which shows an idealized negative voltage

converter. Capacitor C1 is charged to a voltage, VCC, for the half cycle when switches S1 and S3 are closed.

(Note: Switches S2 and S4 are open during this half cycle.) During the second half cycle of operation, switches

S2 and S4 are closed, with S1 and S3 open, thereby shifting capacitor C1 negatively by VCC volts. Charge is then

transferred from C1 to C2 such that the voltage on C2 is exactly VCC, assuming ideal switches and no load on C2.

The TL7660 approaches this ideal situation more closely than existing non-mechanical circuits. In the TL7660,

the four switches of Figure 2 are MOS power switches: S1 is a p-channel device, and S2, S3, and S4 are

n-channel devices. The main difficulty with this design is that in integrating the switches, the substrates of S3

and S4 must always remain reverse biased with respect to their sources, but not so much as to degrade their

ON resistances. In addition, at circuit start up and under output short circuit conditions (VOUT = VCC), the output

voltage must be sensed and the substrate bias adjusted accordingly. Failure to accomplish this results in high

power losses and probable device latchup. This problem is eliminated in the TL7660 by a logic network which

senses the output voltage (VOUT) together with the level translators and switches the substrates of S3 and S4 to

the correct level to maintain necessary reverse bias.

The voltage regulator portion of the TL7660 is an integral part of the anti-latchup circuitry; however, its inherent

voltage drop can degrade operation at low voltages. Therefore, to improve low-voltage operation, the LV

terminal should be connected to GND, disabling the regulator. For supply voltages greater than 3.5 V, the LV

terminal must be left open to insure latchup proof operation and prevent device damage.

Figure 2. Idealized Negative-Voltage Converter

7

Submit Documentation Feedback