TLC320AD50CSLASHI datasheet(18/54 Pages) TI2

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2–3

SCLK

DIN

(16-Bit)

DIN

(15+1-Bit)

16 SCLKs

LSB

D15

d15

D14

d14

d0=0

MSB

see Note B

NOTES: A. The 16-bit or (15 + 1)-bit mode is programmed via control register 1.

B. d0 = 0 means no secondary communication request (software secondary communication request control—paragraph 3.2)

Figure 2–3. Timing Sequence of DAC Channel (Primary Communication Only)

During secondary communication, the digital control and configuration data (together with the register address), are

clocked in through DIN. These 16-bits of data are used either to initialize the register, or to read the register content

through DOUT. If a register initialization is not required, a no-operation word (DS15–DS8 are all set to 0) can be used.

If DS13 is set to 1, the content of the control register, specified by DS12–DS8, will be sent out through DOUT during

the same secondary communication (see section 2.1.5). The timing sequence is shown in Figure 2–4.

DIN (16-Bit)

(see Note A)

16 SCLKs

16-Bit DAC Data

16 SCLKs

Primary

Secondary

Primary

DIN

(15 +1-Bit)

15-Bit DAC

Data + D0=1

(see Note B)

128 SCLKs

256 SCLKs

NOTES: A. FC has to be set high for a secondary communication request when 16–bit DAC data format is used (paragraph 3.2).

B. D0 = 1 means secondary communication request (software secondary communication request control—paragraph 3.2).

Figure 2–4. Timing Sequence of DAC Channel (Primary and Secondary Communication)

2.1.4

Serial Interface

The digital serial interface consists of the shift clock (SCLK), the frame-sync signal (FS), the ADC-channel data output

(DOUT), and the DAC-channel data input (DIN). During the primary frame synchronization interval, SCLK clocks the

ADC channel results out through DOUT and clocks 16-bit/(15+1)-bit DAC data in through DIN.

During the secondary frame-sync interval, SCLK clocks the register read data out through DOUT if the read bit (DS13)

is set to 1 and transfers control and device parameter in through DIN. The timing sequence is shown in Figures 2–2

and 2–4.

2.1.5

All register programming occurs during secondary communications through DIN, and data is latched and valid on the

falling edge of SCLK during the frame-sync signal. If the default value for a particular register is desired, that register

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