STM32L4R9ZIT6P datasheet(20/306 Pages) STMICROELECTRONICS

20 / 306 page

Functional overview

STM32L4R5xx, STM32L4R7xx and STM32L4R9xx

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DocID030321 Rev 3

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Proprietary code readout protection (PCROP): a part of the Flash memory can be

protected against read and write from third parties. The protected area is execute-only

and it can only be reached by the STM32 CPU as an instruction code, while all other

accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited:

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In single bank mode, two areas can be selected with 128-bit granularity.

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In dual bank mode, one area per bank can be selected with 64-bit granularity.

An additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or

not when the RDP protection is changed from Level 1 to Level 0.

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:

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Single error detection and correction

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Double error detection

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The address of the ECC fail can be read in the ECC register.

3.5

Embedded SRAM

The STM32L4R5xx, STM32L4R7xx and STM32L4R9xx devices feature 640 Kbytes of

embedded SRAM. This SRAM is split into three blocks:

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192 Kbytes mapped at address 0x2000 0000 (SRAM1).

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64 Kbytes located at address 0x1000 0000 with hardware parity check (SRAM2).

This memory is also mapped at address 0x2003 0000 offering a contiguous address

space with the SRAM1.

This block is accessed through the ICode/DCode buses for maximum performance.

These 64 Kbytes SRAM can also be retained in Standby mode.

The SRAM2 can be write-protected with 1 Kbyte granularity.

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384 Kbytes mapped at address 0x2004 0000 - (SRAM3).

The memory can be accessed in read/write at CPU clock speed with 0 wait states.

STM32L4R9ZIT6P Datasheet(PDF) 20 Page - STMicroelectronics