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STM32L4R9ZIT6P Datasheet(PDF) 39 Page - STMicroelectronics |
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STM32L4R9ZIT6P Datasheet(HTML) 39 Page - STMicroelectronics |
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39 / 306 page ![]() DocID030321 Rev 3 39/306 STM32L4R5xx, STM32L4R7xx and STM32L4R9xx Functional overview 64 interrupt is generated if enabled. LSE failure can also be detected and generated an interrupt. • Clock-out capability: – MCO (microcontroller clock output): it outputs one of the internal clocks for external use by the application – LSCO (low-speed clock output): it outputs LSI or LSE in all low-power modes (except VBAT). Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 120 MHz. |
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