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STM32L4R9ZIT6P Datasheet(PDF) 21 Page - STMicroelectronics |
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STM32L4R9ZIT6P Datasheet(HTML) 21 Page - STMicroelectronics |
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21 / 306 page  DocID030321 Rev 3 21/306 STM32L4R5xx, STM32L4R7xx and STM32L4R9xx Functional overview 64 3.6 Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, DMA2D, SDMMC1, LCD-TFT and GFXMMU) and the slaves (Flash memory, RAM, FMC, OctoSPI, AHB and APB peripherals). It also ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. Figure 2. Multi-AHB bus matrix 3.7 Firewall These devices embed a firewall which protects code sensitive and secure data from any access performed by a code executed outside of the protected areas. Each illegal access generates a reset which kills immediately the detected intrusion. MSv38490V1 CORTEX ®-M4 with FPU DMA1 DMA2 FSMC AHB2 peripherals AHB1 peripherals SRAM2 SRAM1 FLASH 2 MB ICode DCode OCTOSPI2 DMA2D BusMatrix-S LCD-TFT SDMMC1 GFXMMU SRAM3 GFXMMU OCTOSPI1 |
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