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STM32L496QGI3 Datasheet(PDF) 56 Page - STMicroelectronics

Part # STM32L496QGI3
Description  Ultra-low-power ARM® Cortex®-M4 32-bit MCUFPU, 100DMIPS, up to 1MB Flash, 320KB SRAM, USB OTG FS, audio, ext. SMPS
PDF  262 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L496QGI3 Datasheet(HTML) 56 Page - STMicroelectronics

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Functional overview
STM32L496xx
56/262
DocID029173 Rev 1
3.34
Single wire protocol master interface (SWPMI)
The Single wire protocol master interface (SWPMI) is the master interface corresponding to
the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The
main features are:
•
full-duplex communication mode
•
automatic SWP bus state management (active, suspend, resume)
•
configurable bitrate up to 2 Mbit/s
•
automatic SOF, EOF and CRC handling
SWPMI can be served by the DMA controller.
3.35
Controller area network (CAN)
The two CANs are compliant with the 2.0A and B (active) specifications with a bit rate up to
1Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). 256 bytes of SRAM are allocated for each CAN.
Table 13. SAI implementation
SAI features(1)
1. X: supported
SAI1
SAI2
I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97
X
X
Mute mode
X
X
Stereo/Mono audio frame capability.
X
X
16 slots
X
X
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit
X
X
FIFO Size
X (8 Word)
X (8 Word)
SPDIF
X
X



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