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STM32L496QGI3 Datasheet(PDF) 33 Page - STMicroelectronics

Part # STM32L496QGI3
Description  Ultra-low-power ARM® Cortex®-M4 32-bit MCUFPU, 100DMIPS, up to 1MB Flash, 320KB SRAM, USB OTG FS, audio, ext. SMPS
PDF  262 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L496QGI3 Datasheet(HTML) 33 Page - STMicroelectronics

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STM32L496xx
Functional overview
60
3.10.5
Reset mode
In order to improve the consumption under reset, the I/Os state under and after reset is
“analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is
deactivated when the reset source is internal.
3.10.6
VBAT operation
The VBAT pin allows to power the device VBAT domain from an external battery, an external
supercapacitor, or from VDD when no external battery and an external supercapacitor are
present. The VBAT pin supplies the RTC with LSE and the backup registers. Three anti-
tamper detection pins are available in VBAT mode.
VBAT operation is automatically activated when VDD is not present.
SysTick timer
O
O
O
O
-
--
--
--
--
Touch sensing
controller (TSC)
O
OOO
-
--
--
--
--
Random number
generator (RNG)
O(8)
O(8)
--
-
--
--
--
--
CRC calculation unit
O
O
O
O
-
--
--
--
--
GPIOs
O
OOO
O
OO
O
(9)
5
pins
(10)
(11)
5
pins
(10)
-
1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available.
2. The Flash can be configured in power-down mode. By default, it is not in power-down mode.
3. The SRAM clock can be gated on or off.
4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register.
5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by
the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not
need it anymore.
6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or
received frame event.
7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
8. Voltage scaling Range 1 only.
9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.
11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.
Table 5. Functionalities depending on the working mode(1) (continued)
Peripheral
Run
Sleep
Low-
power
run
Low-
power
sleep
Stop 0/1
Stop 2
Standby Shutdown
VBAT
-
-
-
-



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