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STM32L496QGI3 Datasheet(PDF) 43 Page - STMicroelectronics |
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STM32L496QGI3 Datasheet(HTML) 43 Page - STMicroelectronics |
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43 / 262 page ![]() DocID029173 Rev 1 43/262 STM32L496xx Functional overview 60 This digital interface supports the following features: • Up to two DAC output channels • 8-bit or 12-bit output mode • Buffer offset calibration (factory and user trimming) • Left or right data alignment in 12-bit mode • Synchronized update capability • Noise-wave generation • Triangular-wave generation • Dual DAC channel independent or simultaneous conversions • DMA capability for each channel • External triggers for conversion • Sample and hold low-power mode, with internal or external capacitor The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. 3.19 Voltage reference buffer (VREFBUF) The STM32L496xx devices embed an voltage reference buffer which can be used as voltage reference for ADCs, DACs and also as voltage reference for external components through the VREF+ pin. The internal voltage reference buffer supports two voltages: • 2.048 V • 2.5 V An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer is off. The VREF+ pin is double-bonded with VDDA on some packages. In these packages the internal voltage reference buffer is not available. Figure 5. Voltage reference buffer |
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