STM32L496QGI3 datasheet(188/262 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32L496xx

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DocID029173 Rev 1

Figure 33. 12-bit buffered / non-buffered DAC

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly

without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the

DAC_CR register.

4. Ton is the Refresh phase duration. Toff is the Hold phase duration. Refer to RM0351 reference manual for more details.

Table 82. DAC accuracy(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

DNL

Differential non

linearity (2)

DAC output buffer ON

±2

LSB

DAC output buffer OFF

±2

monotonicity

10 bits

guaranteed

INL

Integral non

linearity(3)

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ

±4

DAC output buffer OFF

CL ≤ 50 pF, no RL

±4

Offset

Offset error at

code 0x800(3)

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ

VREF+ = 3.6 V

±12

VREF+ = 1.8 V

±25

DAC output buffer OFF

CL ≤ 50 pF, no RL

±8

Offset1

Offset error at

code 0x001(4)

DAC output buffer OFF

CL ≤ 50 pF, no RL

±5

OffsetCal

Offset Error at

code 0x800

after calibration

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ

VREF+ = 3.6 V

±5

VREF+ = 1.8 V

±7

Gain

Gain error(5)

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ

±0.5

DAC output buffer OFF

CL ≤ 50 pF, no RL

±0.5

STM32L496QGI3 Datasheet(PDF) 188 Page - STMicroelectronics

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