REFERENCE CIRCUIT DESIGN

CLOCKING

REF

T

REF

B

I

SET

0.1

µF

2.2

µF

2

Ω

56.2k

Ω

2

Ω

2.2

µF

0.1

µF

ADS5271

ADS5271

www.ti.com...................................................................................................................................................... SBAS313C – JUNE 2004 – REVISED JANUARY 2009

The device also supports the use of external

reference voltages. This mode involves forcing REFT

The digital beam-forming algorithm relies heavily on

and REFB externally. In this mode, the internal

gain matching across all receiver channels. A typical

reference buffer is tri-stated. Since the switching

system would have about 12 octal ADCs on the

current for the eight ADCs come from the externally

board. In such a case, it is critical to ensure that the

forced references, it is possible for the performance

gain is matched, essentially requiring the reference

to be slightly less than when the internal references

voltages seen by all the ADCs to be the same.

are used. It should be noted that in this mode, VCM

Matching references within the eight channels of a

and ISET continue to be generated from the internal

chip is done by using a single internal reference

bandgap voltage, as in the internal reference mode. It

voltage buffer. Trimming the reference voltages on

is

therefore

important

to

ensure

that

the

each chip during production ensures the reference

common-mode

voltage

of

the

externally

forced

voltages are well matched across different chips.

reference voltages matches to within 50mV of VCM.

The state of the reference voltages during various

All bias currents required for the internal operation of

combinations of PD and INT/EXT is shown in

the device are set using an external resistor to

Table 1.

ground at pin ISET. Using a 56.2kΩ resistor on ISET

generates an internal reference current of 20

µA. This

Table 1. State of Reference Voltages for Various

current is mirrored internally to generate the bias

Combinations of PD and INT/EXT

current for the internal blocks. Using a larger external

resistor at ISET reduces the reference bias current and

PD

0

0

1

1

thereby scales down the device operating power.

INT/EXT

0

1

0

1

However, it is recommended that the external resistor

REFT

Tri-State

1.95V

Tri-State

Tri-State

be within 10% of the specified value of 56.2k

Ω so

REFB

Tri-State

0.95V

Tri-State

Tri-State

that the internal bias margins for the various blocks

are proper.

VCM

1.45V

1.45V

Tri-State(1)

Tri-State(1)

Buffering the internal bandgap voltage also generates

(1) Weak pull-down (approximately 5k

Ω) to ground.

a voltage called VCM, which is set to the midlevel of

REFT and REFB, and is accessible on a pin. It is

meant as a reference voltage to derive the input

common-mode in case the input is directly coupled. It

The eight channels on the chip operate from a single

can

also

be

used

to

derive

the

reference

ADCLK input. To ensure that the aperture delay and

common-mode voltage in the external reference

jitter are same for all the channels, a clock tree

mode.

network is used to generate individual sampling

clocks to each channel. The clock paths for all the

When using the internal reference mode, a 2

Ω

channels are matched from the source point all the

resistor should be added between the reference pins

way to the sample-and-hold amplifier. This ensures

(REFT and REFB) and the decoupling capacitor, as

that the performance and timing for all the channels

shown in Figure 17. If the device is used in the

are identical. The use of the clock tree for matching

external reference mode, this 2

Ω resistor is not

introduces an aperture delay, which is defined as the

required.

delay between the rising edge of ADCLK and the

actual instant of sampling. The aperture delays for all

the channels are matched to the best possible extent.

However, a mismatch of ±20ps (±3

σ) could exist

between the aperture instants of the eight ADCs

within the same chip. However, the aperture delays of

ADCs across two different chips can be several

hundred

picoseconds

apart.

Another

critical

specification is the aperture jitter that is defined as

the uncertainty of the sampling instant. The gates in

the clock path are designed to provide an rms jitter of

approximately 1ps.

Ideally, the input ADCLK should have a 50% duty

cycle. However, while routing ADCLK to different

components onboard, the duty cycle of the ADCLK

reaching the ADS5271 could deviate from 50%. A

smaller (or larger) duty cycle reduces the time

available for sample or hold phases of each circuit,

Figure 17. Internal Reference Mode

and is therefore not optimal. For this reason, the

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