LVDS BUFFERS

NOISE COUPLING ISSUES

External

Termination

Resistor

OUT

P

High

Low

OUT

N

Low

High

ADS5271

SBAS313C – JUNE 2004 – REVISED JANUARY 2009...................................................................................................................................................... www.ti.com

internal PLL is used to generate an internal clock that

The LVDS buffer receives data from a serializer that

has 50% duty cycle. The input sampling instant,

takes the output data from each channel and

however, is determined by the rising edge of the

serializes it into a single data stream. For a clock

external clock and is not affected by jitter in the PLL.

frequency of 50MHz, the data rate output of the

In addition to generating a 50% duty cycle clock for

serializer is 600MBPS. The data comes out LSB first,

the ADC, the PLL also generates a 12x clock that is

with a register programmability that allows it to revert

used by the serializer to convert the parallel data from

to MSB first. The serializer also transmits a 1x clock

the ADC to a serial stream of bits.

and

a

6x

clock.

The

6x

clock

(denoted

as

LCLKP/LCLKN) is meant to synchronize the capture of

The use of the PLL automatically dictates the

the LVDS data.

minimum sample rate to be about 20MSPS. The PLL

also requires the input clock to be free-running. If the

Deskew mode can be enabled as well, using a

input clock is momentarily stopped (for a duration of

register setting. This mode gives out a data stream of

less than 300ns) then the PLL would require

alternate 0s and 1s and can be used determine the

approximately 10

µs to lock back to the input clock

relative delay between the 6x clock and the output

frequency.

data for optimum capture. A 1x clock is also

generated by the serializer and transmitted through

the LVDS buffer. The 1x clock (referred to as

ADCLKP/ADCLKN) is used to determine the start of

The LVDS buffer has two current sources, as shown

the 12-bit data frame. Sync mode (enabled through a

in Figure 18. OUTP and OUTN are loaded externally

register setting) gives out a data of six 0s followed by

by a resistive load that is ideally about 100

Ω.

six 1s. Using this mode, the 1x clock can be used to

Depending on whether the data is 0 or 1, the currents

determine the start of the data frame. In addition to

are directed in one direction or the other through the

the deskew mode pattern and the sync mode pattern,

resistor. The LVDS buffer has four current settings.

a custom pattern can be defined by the user and

The default current setting is 3.5mA, and provides a

output from the LVDS buffer. The LVDS buffers are

differential drop of about ±350mV across the 100

Ω

tri-stated in the power-down mode. The LVDS outputs

resistor.

are weakly forced to 1.2V through 10k

Ω resistors

(from each output pin to 1.2V).

High-speed mixed signals are sensitive to various

types of noise coupling. One of the main sources of

noise is the switching noise from the serializer and

the output buffers. Maximum care is taken to isolate

these noise sources from the sensitive analog blocks.

As a starting point, the analog and digital domains of

the chip are clearly demarcated. AVDD and AVSS

are used to denote the supplies for the analog

sections, while LVDD and LVSS are used to denote

the digital supplies. Care is taken to ensure that there

is minimal interaction between the supply sets within

the

device.

The

extent

of

noise

coupled

and

transmitted from the digital to the analog sections

depends on the following:

1. The

effective

inductances

of

each

of

the

supply/ground sets.

2. The isolation between the digital and analog

Figure 18. LVDS Buffer

supply/ground sets.

Smaller effective inductance of the supply/ground

The single-ended output impedance of the LVDS

pins leads to better suppression of the noise. For this

drivers is very high because they are current-source

reason,

multiple

pins

are

used

to

drive

each

driven. If there are excessive reflections from the

supply/ground. It is also critical to ensure that the

receiver, it might be necessary to place a 100

Ω

impedances of the supply and ground lines on board

termination resistor across the outputs of the LVDS

drivers to minimize the effect of reflections. In such a

situation, the output current of the LVDS drivers can

be increased to regain the output swing.

20

Submit Documentation Feedback

Copyright © 2004–2009, Texas Instruments Incorporated

Product Folder Link(s): ADS5271