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TIMING REQUIREMENTS

(1) (2) (3) (4) (5) (6)

ADS8370

SLAS450 – JUNE 2005

ADS8370I/ADS8370IB

REF

PARAMETER

UNIT

FIGURE

MIN

TYP

MAX

tconv

Conversion time

1000

1160

ns

41 – 44

tacq1

Acquisition time in normal mode

0.5

µs

41,42,44

tacq2

Acquisition time in nap mode (tacq2 = tacq1 + td18)

0.8

µs

43

CONVERSION AND SAMPLING

Quite sampling time (last toggle of interface signals to convert start

40 – 43,

tquiet1

30

ns

command)(6)

45 – 47

Quite sampling time (convert start command to first toggle of interface

40 – 43,

tquiet2

10

ns

signals)(6)

45 – 47

Quite conversion time (last toggle of interface signals to fall of BUSY)(6)

40 – 43,

tquiet3

600

ns

45,47

tsu1

Setup time, CONVST before BUSY fall

15

ns

41

tsu2

Setup time, CS before BUSY fall (only for conversion/sampling control)

20

ns

40,41

tsu4

Setup time, CONVST before CS rise (so CONVST can be recognized)

5

ns

41,43,44

th1

Hold time, CS after BUSY fall (only for conversion/sampling control)

0

ns

41

th3

Hold time, CONVST after CS rise

7

ns

43

th4

Hold time, CONVST after CS fall (to ensure width of CONVST_QUAL)(4)

20

ns

42

tw1

CONVST pulse duration

20

ns

43

tw2

CS pulse duration

10

ns

41,42

Pulse duration, time between conversion start command and conversion

tw5

1000

ns

44

abort command to successfully abort the ongoing conversion

DATA READ OPERATION

tcyc

SCLK period

25

ns

45 – 47

SCLK duty cycle

40%

60%

tsu5

Setup time, CS fall before first SCLK fall

10

ns

45

tsu6

Setup time, CS fall before FS rise

7

ns

46,47

tsu7

Setup time, FS fall before first SCLK fall

7

ns

46,47

th5

Hold time, CS fall after SCLK fall

3

ns

45

th6

Hold time, FS fall after SCLK fall

7

ns

46,47

tsu2

Setup time, CS fall before BUSY fall (only for read control)

20

ns

40,45

tsu3

Setup time, FS fall before BUSY fall (only for read control)

20

ns

40,47

th2

Hold time, CS fall after BUSY fall (only for read control)

15

ns

40,45

th8

Hold time, FS fall after BUSY fall (only for read control)

15

ns

40,47

tw2

CS pulse duration

10

ns

45

tw3

FS pulse duration

10

ns

46,47

MISCELLANEOUS

tw4

PD pulse duration for reset and power down

60

ns

53,54

All unspecified pulse durations

10

ns

(1)

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

(2)

All specifications typical at –40°C to 85°C, +VA = +4.75 V to +5.25 V, +VBD = +2.7 V to +5.25 V.

(3)

All digital output signals loaded with 10-pF capacitors.

(4)

CONVST_QUAL is CONVST latched by a low value on CS (see Figure 39).

(5)

Reference figure indicated is only a representative of where the timing is applicable and is not exhaustive.

(6)

Quiet time zones are for meeting performance and not functionality.

5

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