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TIMING CHARACTERISTICS

(1) (2) (3) (4)

ADS8370

SLAS450 – JUNE 2005

ADS8370I/ADS8370IB

REF

PARAMETER

UNIT

FIGURE

MIN

TYP

MAX

CONVERSION AND SAMPLING

td1

Delay time, conversion start command to conversion start (aperture delay)

10

ns

41,43

td2

Delay time, conversion end to BUSY fall

5

ns

41 – 43

td4

Delay time, conversion start command to BUSY rise

20

ns

41

td3

Delay time, CONVST rise to sample start

5

ns

43

td5

Delay time, CS fall to sample start

10

ns

43

td6

Delay time, conversion abort command to BUSY fall

10

ns

44

DATA READ OPERATION

td12 Delay time, CS fall to MSB valid

3

15

ns

45

td15 Delay time, FS rise to MSB valid

6

18

ns

46,47

td7

Delay time, BUSY fall to MSB valid (if FS is high when BUSY falls)

18

ns

47

td13 Delay time, SCLK rise to bit valid

2

10

ns

45– 47

td14 Delay time, CS rise to SDO 3-state

6

ns

45

MISCELLANEOUS

td10 Delay time, PD rise to SDO 3-state

55

ns

53,54

Nap mode

300

ns

55

Delay time, total

Full power down (external reference used with or without

td11 + 2x

54

td18 device resume

1-µF||0.1-µF capacitor on REFOUT)

conversions

time

Full power down (internal reference used with or without

25(4)

ms

53

1-µF||0.1-µF capacitor on REFOUT)

td11 Delay time, untrimmed circuit full power-down resume time

1

ms

53,54

Delay time, device

Nap

200

ns

55

td16 power-down time

Full power down (internal/external reference used)

10

µs

53,54

Delay time, trimmed internal reference settling (either by turning on supply or

td17

4

ms

53

resuming from full power-down mode), with 1-µF||0.1-µF capacitor on REFOUT

(1)

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

(2)

All specifications typical at –40°C to 85°C, +VA = +4.75 V to +5.25 V, +VBD = +2.7 V to +5.25 V.

(3)

All digital output signals loaded with 10-pF capacitors.

(4)

Including td11, two conversions (time to cycle CONVST twice), and td17.

6

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