IN+B

IN+A

OUT+A

OUT+B

1

GND

2

IN–B

1

IN–B

1

IN–B

2

OUTB

2

OUTB

1

+3.3V

2

GND

1

GND

2

IN–A

1

IN–A

1

IN–A

2

OUTA

2

OUTA

LM7332

www.ti.com

SNOSAV4B – APRIL 2008 – REVISED JANUARY 2016

10 Layout

10.1 Layout Guidelines

Take care to minimize the loop area formed by the bypass capacitor connection between supply pins and

ground. A ground plane underneath the device is recommended; any bypass components to ground must have a

nearby via to the ground plane. The optimum bypass capacitor placement is closest to the corresponding supply

pin. Use of thicker traces from the bypass capacitors to the corresponding supply pins lowers the power supply

inductance and provide a more stable power supply.

The feedback components must be placed as close to the device as possible to minimize stray parasitics.

10.2 Layout Example

Figure 53. LM7332 Layout Example

10.3 Output Short Circuit Current and Dissipation Issues

The LM7332 output stage is designed for maximum output current capability. Even though momentary output

shorts to ground and either supply can be tolerated at all operating voltages, longer-lasting short conditions can

cause the junction temperature to rise beyond the absolute maximum rating of the device, especially at higher

supply voltage conditions. Below a supply voltage of 6 V, the output short circuit condition can be tolerated

indefinitely.

With the operational amplifier tied to a load, the device power dissipation consists of the quiescent power due to

the supply current flow into the device, in addition to power dissipation due to the load current. The load portion

of the power itself could include an average value (due to a DC load current) and an AC component. DC load

current would flow if there is an output voltage offset, or the output AC average current is non-zero, or if the

operational amplifier operates in a single-supply application where the output is maintained somewhere in the

range of linear operation.

Therefore,

PTOTAL = PQ + PDC + PAC

(5)

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