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TAS3202 Datasheet(PDF) 21 Page - Texas Instruments

Part # TAS3202
Description  AUDIO DSP WITH ANALOG INTERFACE
PDF  69 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

TAS3202 Datasheet(HTML) 21 Page - Texas Instruments

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Address
Decoder
D
WE
CCLK
D
WE
8051 MCU
DESTIN_DO
DESTIN_A
SFRWE
SFRWA
ESFRDI
Internal
Data
Memory
Bus
Control Out
Control In
CCLK
CCLK
TAS3202
www.ti.com
SLES208B – JUNE 2009 – REVISED MARCH 2011
6.1.1
Register Banks
There are four directly addressable register banks, only one of which may be selected at one time. The
register banks occupy Internal Data Memory addresses from 00 hex to 1F hex.
6.1.2
Bit Addressing
The 16 bytes of Internal Data Memory that occupy addresses from 20 hex to 2F hex are bit addressable.
SFRs that have addresses of the form 1XXXX000 binary are also bit addressable.
6.1.3
External Data Memory
External data memory occupies a 2K × 8 address space. This space contains the ESFRs. The ESFRs
permit access and control of the hardware features and internal interfaces of the TAS3202.
6.1.4
Extended Special Function Registers (ESFRs)
ESFRs provide signals needed for the M8051 to control the different blocks in the device. ESFR is an
extension to the M8051. Figure 6-2 shows how these registers are arranged.
Figure 6-2. ESFRs
6.1.5
Memory-Mapped Registers for DAP Data Memory
The following memory mapped registers are used for communication with the DAP.
Table 6-1. Memory-Mapped Registers
ADDRESS
REGISTER
COMMENT
0x0300
Dither Seed
Sets the dither seed value
0x0301
PC Start
Sets the starting address of the DAP
0x0302
Reserved
Reserved
NOTE
TAS3202 has the same memory mapped registers distinction of upper and lower memory for
these registers.
6.2
General I
2C Operations
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated
circuits in a system. Data is transferred on the bus serially one bit at a time. The address and data are
transferred in byte (8-bit) format with the MSB transferred first. In addition, each byte transferred on the
Copyright © 2009–2011, Texas Instruments Incorporated
Microprocessor Controller
21
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