TAS3202 datasheet(8/69 Pages) TI2

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TAS3202

SLES208B – JUNE 2009 – REVISED MARCH 2011

www.ti.com

3.2

Terminal Descriptions

TERMINAL

INPUT/

PULLUP/

DESCRIPTION

OUTPUT(1)

PULLDOWN(2)

NAME

NO.

AIN1LM

Analog input

Pull to VMID(3)

Analog input, channel 1, left, – input

AIN1LP

Analog input

Analog input, channel 1, left, + input

AIN1RM

Analog input

Pull to VMID(3)

Analog input, channel 1, right, – input

AIN1RP

Analog input

Analog input, channel 1, right, + input

AIN2LM

Analog input

Pull to VMID(3)

Analog input, channel 2, left, – input

AIN2LP

Analog input

Analog input, channel 2, left, + input

AIN2RM

Analog input

Pull to VMID(3)

Analog input, channel 2, right, – input

AIN2RP

Analog input

Analog input, channel 2, right, + input

AOUTLM

Analog output

Analog output, channel 1, left, – output

AOUTLP

Analog output

Analog output, channel 1, left, + output

AOUTRM

Analog output

Analog output, channel 1, right, – output

AOUTRP

Analog output

Analog output, channel 1, right, + output

3.3-V analog power supply. This pin must be decoupled according to

AVDD1

Power

good design practices.

AVSS1

Power

Analog supply ground

3.3-V analog power supply. This pin must be decoupled according to

AVDD2

Power

good design practices.

AVSS2

Power

Analog supply ground

3.3-V analog power supply. This pin must be decoupled according to

AVDD3

Power

good design practices.

AVSS3

Power

Analog supply ground

CS0

Digital input

I2C Chip select

3.3-V digital power supply. This pin must be decoupled according to

DVDD1

Power

good design practices.

DVSS1

Power

Digital supply ground

3.3-V digital power supply. This pin must be decoupled according to

DVDD2

Power

good design practices.

DVSS2

Power

Digital supply ground

3.3-V digital power supply. This pin must be decoupled according to

DVDD3

Power

good design practices.

DVSS3

Power

Digital supply ground

GPIO1

Digital I/O

General-purpose input/output

GPIO2

Digital I/O

General-purpose input/output

Slave I2C serial clock input/output. Normally connected to the system

I2C1_SCL

Digital I/O

microprocessor.

Slave I2C serial control data interface input/output. Normally connected

I2C1_SDA

Digital I/O

to system micro.

I2C2_SCL

Digital output

Master I2C serial clock output. Normally connected to EEPROM.

Master I2C serial control data interface input/output. Normally

I2C2_SDA

Digital I/O

connected to EEPROM.

LRCLK_IN

Digital input

Pulldown

Serial data input left/right clock for I2S interface

LRCLK_OUT

Digital output

Serial data output left/right clock for I2S interface

MCLK input is used in slave mode. MCLK_IN must be locked to

MCLK_IN

Digital input

Pulldown

LRCLK_IN, and the frequency is 512Fs (24.576 MHz for 48-kHz Fs).

MCLK_OUT1

Digital output

12.288-MHz clock output. This output is valid even when reset is LOW.

(1)

I = input; O = output

(2)

All pullups are 20-

μA weak pullups, and all pulldowns are 20-μA weak pulldowns. The pullups and pulldowns are included to ensure

proper input logic levels if the terminals are left unconnected (pullups

→ logic 1 input; pulldowns → logic 0 input). Devices that drive

inputs with pullups must be able to sink 20

μA while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be

able to source 20

μA while maintaining a logic-1 drive level.

(3)

Pull to VMID when analog input is in single-ended mode.

Physical Characteristics

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