A6

A5

A4

A3

A2

A1

A0

R/W ACK A7

A6

A5

A4

A3

A2

A1

A0

ACK

D7

D6

D5

D4

D3

D2

D1

D0 ACK

Start

Condition

Stop

Condition

Acknowledge

Acknowledge

Acknowledge

I CDevice Addressand

2

Read/WriteBit

Subaddress

DataByte

T0036-01

MULTIPLE-BYTE WRITE AND INCREMENTAL MULTIPLE-BYTE WRITE

D7

D0 ACK

Stop

Condition

Acknowledge

I CDevice Addressand

2

Read/WriteBit

Subaddress

LastDataByte

A6

A5

A1

A0 R/W ACK A7

A5

A1

A0

ACK D7

ACK

Start

Condition

Acknowledge

Acknowledge

Acknowledge

FirstDataByte

A4

A3

A6

OtherDataBytes

ACK

Acknowledge

D0

D7

D0

T0036-02

SINGLE-BYTE READ

TAS5086

SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.com

Figure 23. Single-Byte Write Transfer

A multiple-byte data write transfer is identical to a single-byte data write transfer, except that multiple data bytes

are transmitted by the master device to TAS5086 as shown in Figure 24. After receiving each data byte, the

TAS5086 responds with an acknowledge bit.

Figure 24. Multiple-Byte Write Transfer

The I2C supports a special mode that permits I2C write operations to be broken up into multiple data write

operations that are multiples of 4 data bytes. These are 6-, 10-, 14-, 18-, ..., etc., -byte write operations that are

composed of a device address, read/write bit, and subaddress and any multiple of 4 bytes of data. This permits

the system to write large register values incrementally without blocking other I2C transactions.

This feature is enabled by the append subaddress (0xFE) in the TAS5086. The append address, 0xFE, enables

the TAS5086 to append an integer number of 4-, 8-, 12-, 16-, … byte blocks of data to a register that was

opened by a previous I2C register write operation, but has not received its complete number of data bytes.

When the correct number of bytes has been received, the TAS5086 starts processing the data.

The procedure to perform a multiple-byte write operation is as follows.

1. Start a normal I2C write operation by sending the device address, write bit, register subaddress, and an

integer number of 4-byte data blocks. At the end of that sequence, a stop condition is sent.

At this point the register has been opened. It then accepts the remaining data sent by one or more write

operations, consisting of an integer number of 4-byte blocks. This data should be written to the append

subaddress (0xFE).

2. At a later time, one or more append data transfers are performed to incrementally transfer the remaining

number of bytes in sequential order to complete the register write operation. Each of these append

operations is composed of the device address, write bit, append subaddress (0xFE), and an integer number

of four bytes of data, followed by a stop condition.

3. The operation is terminated due to an error condition, and the data is flushed:

–

If a new subaddress is written to the TAS5086 before the correct number of bytes has been written

–

If a noninteger number of 4 bytes is written at the beginning or during any of the append operations

–

If a read bit is sent

As shown in Figure 25, a single-byte data read transfer begins with the master device transmitting a start

condition, followed by the I2C device address and the read/write bit. For the data read transfer, both a write

followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal

24

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