TAS5086

www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008

Table 1. TERMINAL FUNCTIONS (continued)

TERMINAL

5-V

I/O(1)

TERMINATION(2)

DESCRIPTION

TOLERANT

NAME

NO.

Power down, active-low. PDN powers down all logic, stops all clocks, and

performs a soft stop whenever a logic low is applied. The internal

parameters are preserved through a power-down cycle, as long as RESET

PDN

10

DI

5-V

Pullup

is not active. The duration for system recovery from power down is 100

ms. When released, PDN powers up all logic, starts all clocks, and

performs a soft start that returns to the previous configuration.

PLL_FLTM

5

AO

PLL negative input

PLL_FLTP

6

AI

PLL positive input

PWM_ 1

38

DO

PWM 1 output

PWM_ 2

37

DO

PWM 2 output

PWM_ 3

36

DO

PWM 3 output

PWM_ 4

35

DO

PWM 4 output

PWM_ 5

34

DO

PWM 5 output

PWM_ 6

33

DO

PWM 6 output

RESERVED

21

–

RESERVED (connect to ground)

A system reset is generated by applying a logic low to this terminal.

RESET is an asynchronous control signal that restores the TAS5086 to its

default conditions, sets the VALID2 output low, and places the PWM in the

RESET

9

DI

5-V

Pullup

hard-mute (M) state. Master volume is immediately set to full attenuation.

On the release of RESET, if PDN is high, the system performs a 4–5-ms

device initialization and sets the volume at mute.

SCL

18

DI

5-V

I2C serial control clock input

Serial audio data clock (shift clock). SCLKIN is the serial audio port (SAP)

SCLK

20

DI

5-V

Pulldown

input data bit clock.

SDA

17

DIO

5-V

I2C serial control data interface input/output

Serial audio data 1 input is one of the serial data input ports. SDIN1

SDIN1

26

DI

Pulldown

supports four discrete (stereo) data formats.

Serial audio data 2 input is one of the serial data input ports. SDIN2

SDIN2

25

DI

Pulldown

supports four discrete (stereo) data formats.

Serial audio data 3 input is one of the serial data input ports. SDIN3

SDIN3

24

DI

Pulldown

supports four discrete (stereo) data formats.

Serial audio data 4 input is one of the serial data input ports. SDIN4

SDIN4

23

DI

Pulldown

supports four discrete (stereo) data formats.

Serial audio data 1 output is the only serial data output port. SDOUT

SDOUT

22

DI

supports I2S format only.

Soft start valid. Output indicating validity of soft-start PWM output,

VALID1

31

DO

active-high

VALID2

32

DO

Output indicating validity of PWM outputs, active-high.

Voltage reference for analog supply, 1.8 V. A pinout of the internally

regulated 1.8-V power. A 0.1-

µF, low-ESR capacitor should be connected

VR_ANA

1

P

between this terminal and AVSS_PLL. This terminal must not be used to

power external devices.

Voltage reference for digital PWM core supply, 1.8 V. A pinout of the

internally regulated 1.8-V power used by digital PWM core logic. A 0.1-

µF,

VR_DIG

30

P

low-ESR(3) capacitor should be connected between this terminal and

DVSS_PWM. This terminal must not be used to power external devices.

Voltage reference for analog supply, 1.8 V. A pinout of the internally

regulated 1.8-V power. A 0.1-

µF, low-ESR(3) capacitor should be

VR_OSC

15

P

connected between this terminal and AVSS_PLL. This terminal must not

be used to power external devices.

(3)

If desired, low-ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling

capacitors of equal value provides an extended high-frequency supply decoupling. This approach avoids the potential of producing

parallel resonance circuits that have been observed when paralleling capacitors of different values.

Copyright © 2005–2008, Texas Instruments Incorporated

Submit Documentation Feedback

9

Product Folder Link(s): TAS5086