Chan.

1 − 6

1− 5

SDIN1

SDIN2

SDIN3

SDIN4

SDA

SCL

PWM1

PWM2

PWM3

PWM4

PWM5

PWM6

VALID1

DVDD

DVSS

DVSS_ESD

VR_DIG

VR_ANA

VR_OSC

AVDD

AVSS_PLL

SDOUT

MCLK

SCLK

LRCLK

PLLFLTP

PLLFLTM

HFCLK

OSCFLT

OSC_RES

1 LF

2 RF

3 LS

4 RS

5 C

1− 6

L’

R’

L’

R’

(L’+R’) / 2

VALID2

1 − 5

Ch

1−6

6

6

6

6

6

6

SDIN4

SDIN4

Downmix

PWM

Control

PDN

RESET

MUTE

VREG_EN

BKNDERR

Channel Six Processing

Bass Management

B0080-01

Power

Supply

Serial

Data

Interface

Channel

Selector

Block

MUX

MUX

Down−

mix

Clock Rate

/Error

Detection

and PLL

Serial

Control

Interface

System

Control

MUX

I2S Serial

Output

MUX

MUX

MUX

Vol

PWM

MUX

MUX

MUX

MUX

MUX

(L’+R’)/2

TAS5086

www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008

Figure 1. TAS5086 Functional Block Diagram

Copyright © 2005–2008, Texas Instruments Incorporated

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