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TDP142 Datasheet(PDF) 17 Page - Texas Instruments

Part # TDP142
Description  TDP142 DisplayPortTM 8.1 Gbps Linear Redriver
PDF  36 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

TDP142 Datasheet(HTML) 17 Page - Texas Instruments

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TDP142
www.ti.com
SLLSEZ1C – SEPTEMBER 2017 – REVISED MAY 2019
Product Folder Links: TDP142
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
8.6 Register Maps
8.6.1 General Register (address = 0x0A) [reset = 00000001]
Figure 11. General Registers
7
6
5
4
3
2
1
0
Reserved
SWAP_HPDIN
EQ_OVERRID
E
HPDIN_OVRRI
DE
Reserved.
CTLSEL[1:0].
R
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6. General Registers
Bit
Field
Type
Reset
Description
7:6
Reserved
R
00
Reserved.
5
SWAP_HPDIN
R/W
0
0 – HPDIN is in default location (Default)
1 – HPDIN location is swapped (PIN 23 to PIN 32, or PIN 32 to
PIN 23).
4
EQ_OVERRIDE
R/W
0
Setting of this field will allow software to use EQ settings from
registers instead of value sample from pins.
0 – EQ settings based on sampled state of the EQ pins
(DPEQ[1:0]).
1 – EQ settings based on programmed value of each of the EQ
registers
3
HPDIN_OVRRIDE
R/W
0
0 – HPD based on state of HPDIN pin (Default)
1 – HPD high.
2
Reserved
R/W
0
Reserved.
1:0
CTLSEL[1:0]
R/W
01
Upon power-on, software must write 2'b10 to enable DisplayPort
functionality. If DisplayPort functionality is not required, then
software must write 2'b00 to disable DisplayPort.
00 - Shutdown. DP disabled and lowest power state.
01 - DP disabled but not in lowest power state.
10 - DP enabled
11 - Reserved.
8.6.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
Figure 12. DisplayPort Control/Status Registers (0x10)
7
6
5
4
3
2
1
0
DP1EQ_SEL
DP0EQ_SEL
R/W/U
R/W/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7. DisplayPort Control/Status Registers (0x10)
Bit
Field
Type
Reset
Description
7:4
DP1EQ_SEL
R/W/U
0000
Field selects between 0 to 14dB of EQ for DP lane 1. When
EQ_OVERRIDE = 1’b0, this field reflects the sampled state of
DPEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can
change the EQ setting for DP lane 1 based on value written to
this field.
3:0
DP0EQ_SEL
R/W/U
0000
Field selects between 0 to 14dB of EQ for DP lane 0. When
EQ_OVERRIDE = 1’b0, this field reflects the sampled state of
DPEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can
change the EQ setting for DP lane 0 based on value written to
this field.



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