TDP142 datasheet(8/36 Pages) TI2

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TDP142

SLLSEZ1C – SEPTEMBER 2017 – REVISED MAY 2019

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6.8 Timing Requirements

MIN

NOM

MAX

UNIT

tDIFF_DLY

Differential Propagation Delay

See Figure 7

300

tR, tF

Output Rise/Fall time (see Figure 9)

20%-80% of differential

voltage measured 1 inch

from the output pin

tRF_MM

Output Rise/Fall time mismatch

20%-80% of differential

voltage measured 1 inch

from the output pin

2.6

6.9 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DPEN and HPDIN

tDPEN_DEBOUNCE

DPEN and HPDIN debounce time when transitioning from H to L.

I2C (Refer to Figure 6)

fSCL

I2C clock frequency

MHz

tBUF

Bus free time between START and STOP conditions

0.5

µs

tHDSTA

Hold time after repeated START condition. After this period, the first

clock pulse is generated

0.26

µs

tLOW

Low period of the I2C clock

0.5

µs

tHIGH

High period of the I2C clock

0.26

µs

tSUSTA

Setup time for a repeated START condition

0.26

µs

tHDDAT

Data hold time

μs

tSUDAT

Data setup time

Rise time of both SDA and SCL signals

120

Fall time of both SDA and SCL signals

20 × (V(I2C)/5.5

120

tSUSTO

Setup time for STOP condition

0.26

μs

Capacitive load for each bus line

150

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