DIX4192 datasheet(24/71 Pages) TI2

24 / 71 page

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DIX4192

SBFS031F – FEBRUARY 2006 – REVISED SEPTEMBER 2016

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Device Functional Modes (continued)

9.4.2 Host Interface Operation: PHILIPS I2C Mode

The DIX4192 supports a 2-wire Philips I2C bus interface when CPM (pin 18) is forced high or pulled up to the

VIO supply rail. The DIX4192 functions as a Slave-only device on the bus. Standard and Fast modes of

operation are supported. Standard mode supports data rates up to 100 kbps, while Fast mode supports data

rates up to 400 kbps. Fast mode is downward compatible with Standard mode, and these modes are sometimes

referred to as Fast/Standard, or F/S mode. The I2C Bus Specification (Version 2.1, January 2000), available from

Philips Semiconductor, provides the details for the bus protocol and implementation. It is assumed that the

reader is familiar with this specification. Refer to the I2C Standard and Fast Modes section of the Electrical

Characteristics table and Figure 3 for specifications and a timing diagram that highlight the key parameters for

I2C interface operation.

When the I2C mode is invoked, pin 20 becomes SCL (which serves as the bus clock) and pin 22 becomes SDA

(which carries the bi-directional serial data for the bus). Pins 19 and 21 become A0 and A1, respectively, and

function as the hardware configurable portion of the 7-bit slave address.

The DIX4192 uses a 7-bit Slave address; see Figure 20(a). Bits A2 through A6 are fixed and bits A0 and A1 are

hardware programmable using pins 19 and 21, respectively. The programmable bits allow for up to four DIX4192

devices to be connected to the same bus. The slave address is followed by the Register Address Byte, which

points to a specific register or data buffer location in the DIX4192 register map. The register address byte is

comprised of seven bits for the address, and one bit for enabling or disabling auto-increment operation; see

Figure 20(b). Auto-increment mode allows multiple sequential register locations to be written to or read back in a

single operation, and is especially useful for block write and read operations.

Figure 21 shows the protocol for Standard and Fast mode Write operations. When writing a single register

address, or multiple non-sequential register addresses, the single register write operation of Figure 21(a) may be

used one or more times. When writing multiple sequential register addresses, the auto-increment mode of

Figure 21(b) improves efficiency. The register address is automatically incremented by one for each successive

byte of data transferred.

Figure 22 shows the protocol for Standard and Fast mode Read operations. The current address read operation

of Figure 22(a) assumes the value of the register address from the previously executed write or read operation,

and is useful for polling a register address for status changes. Figure 22(b) and Figure 22(c) show read

operations for one or more random register addresses, with or without auto-increment mode enabled.

Figure 20. DIX4192 Slave Address and Register Address Byte Definitions

DIX4192 Datasheet(PDF) 24 Page - Texas Instruments

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