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DIX4192 Datasheet(PDF) 12 Page - Texas Instruments

Part # DIX4192
Description  DIX4192 Integrated Digital Audio Interface Receiver and Transmitter
PDF  71 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

DIX4192 Datasheet(HTML) 12 Page - Texas Instruments

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Audio Serial
PortA
Audio Serial
PortB
Digital
Interface
Receiver(DIR)
Digital
Interface
Transmitter
(DIT)
TX+
TX-
SDINA
SDOUTA
LRCKA
BC A
K
SDINB
SDOUTB
LRCKB
BC B
K
CPM
CS or A0
CCLKorSCL
CDINor 1
A
CDOUT orSDA
INT
RST
Host
Interface
(SPIor I C)
2
and
Gene a
r l-
Purp s
o e
Outputs
Master
Cl ck
o
Distribution
MC K
L
RXCKI
FromRXCKO
GP 1
O
GP 2
O
GP 3
O
GP 4
O
AESOUT
RXCKO
LOCK
RX +
2
RX -
2
RX +
3
RX -
3
RX +
4
RX -
4
RX +
1
RX -
1
BLS
SY C
N
ControlandStatus
Registers
DIRCand U
DataBuffers
DITCand U
DataBuffers
DIX4192
Power
VDD18
DGND1
VDD33
DGND2
VIO
DGND3
VCC
AG D
N
BG D
N
InternallyTied
toSubstrate
12
DIX4192
SBFS031F – FEBRUARY 2006 – REVISED SEPTEMBER 2016
www.ti.com
Product Folder Links: DIX4192
Submit Documentation Feedback
Copyright © 2006–2016, Texas Instruments Incorporated
9.2 Functional Block Diagram
9.3 Feature Description
9.3.1 RESET Operation
The DIX4192 includes an asynchronous active low reset input, RST (pin 24), which may be used to initialize the
internal logic at any time. The reset sequence forces all registers and buffers to their default settings. The reset
low pulse width must be a minimum of 500 ns in length. The user must not attempt a write or read operation
using either the SPI or I2C port for at least 500 μs after the rising edge of RST. See Figure 6 for the reset timing
sequence of the DIX4192.
In addition to reset input, the RESET bit in control register 0x01 may be used to force an internal reset, whereby
all registers and buffers are forced to their default settings. Refer to Control Registers for details regarding the
RESET bit function.
Upon reset initialization, all functional blocks of the DIX4192 default to the power-down state, with the exception
of the SPI or I2C host interface and the corresponding control registers. The user may then program the DIX4192
to the desired configuration, and release the desired function blocks from the power-down state using the
corresponding bits in control register 0x01.



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