R2 =

1.25V x R1

VPWR ± 1.25V ± (23 2A x R1)

R1 =

VHYS

23 2A

LM5035

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SNVS428H – JANUARY 2006 – REVISED OCTOBER 2015

The internal gate drivers need a very low impedance path to the respective decoupling capacitors; the VCC cap

for the LO driver and CBOOST for the HO driver. These connections must be as short as possible to reduce

inductance and as wide as possible to reduce resistance. The loop area, defined by the gate connection and its

respective return path, must be minimized.

The high-side gate driver can also be used with HS connected to PGND for applications other than a half bridge

converter (for example, push-pull). The HB pin is then connected to VCC, or any supply greater than the high-

side driver undervoltage lockout (approximately 6.5 V). In addition, the high-side driver can be configured for high

voltage offline applications where the high-side MOSFET gate is driven via a gate drive transformer.

8.2.2.5 Programmable Delay (DLY)

The RDLY resistor programs the delays between the SR1 and SR2 signals and the HO and LO driver outputs.

Figure 14 shows the relationship between these outputs. The DLY pin is nominally set at 2.5 V and the current is

sensed through RDLY to ground. This current is used to adjust the amount of dead time before the HO and LO

pulse (T1) and after the HO and LO pulse (T2). Typically RDLY is in the range of 10 kΩ to 100 kΩ. The dead-time

periods can be calculated using Equation 7 and Equation 8:

T1 = [RDLY × 2.8 ps] + 20 ns

(7)

T2 = [RDLY × 1.35 ps] + 6 ns

(8)

T1 and T2 can be set to minimum by not connecting a resistor to DLY, connecting a resistor greater than 300 k

Ω

from DLY to ground, or connecting DLY to the REF pin. This may cause lower than optimal system efficiency if

the delays through the SR signal transformer network, the secondary gate drivers and the SR MOSFETs are

greater than the delay to turn on the HO or LO MOSFETs. must an SR MOSFET remain on while the opposing

primary MOSFET is supplying power through the power transformer, the secondary winding will experience a

momentary short circuit, causing a significant power loss to occur.

When choosing the RDLY value, worst case propagation delays and component tolerances must be considered to

assure that there is never a time where both SR MOSFETs are enabled AND one of the primary side MOSFETs

is enabled. The time period T1 must be set so that the SR MOSFET has turned off before the primary MOSFET

is enabled. Conversely, T1 and T2 must be kept as low as tolerances allow to optimize efficiency. The SR body

diode conducts during the time between the SR MOSFET turns off and the power transformer begins supplying

energy. Power losses increase when this happens since the body diode voltage drop is many times higher than

the MOSFET channel voltage drop. The interval of body diode conduction can be observed with an oscilloscope

as a negative 0.7 V to 1.5 V pulse at the SR MOSFET drain.

8.2.2.6 UVLO and OVP Voltage Divider Selection for R1, R2, and R3

Two dedicated comparators connected to the UVLO and OVP pins are used to detect undervoltage and

overvoltage conditions. The threshold value of these comparators, VUVLO and VOVP, is 1.25 V (typical). The two

functions can be programmed independently with two voltage dividers from VIN to AGND as shown in Figure 20

and Figure 21, or with a three-resistor divider as shown in Figure 22. Independent UVLO and OVP pins provide

greater flexibility for the user to select the operational voltage range of the system. Hysteresis is accomplished by

23-µA current sources (IUVLO and IOVP), which are switched on or off into the sense pin resistor dividers as the

comparators change state.

When the UVLO pin voltage is below 0.4 V, the controller is in a low current shutdown mode. For a UVLO pin

voltage greater than 0.4 V but less than 1.25 V the controller is in standby mode. Once the UVLO pin voltage is

greater than 1.25 V, the controller is fully enabled. Two external resistors can be used to program the minimum

operational voltage for the power converter as shown in Figure 20. When the UVLO pin voltage falls below the

1.25-V threshold, an internal 23-µA current sink is enabled to lower the voltage at the UVLO pin, thus providing

threshold hysteresis. Resistance values for R1 and R2 can be determined from Equation 9 and Equation 10.

(9)

where

•

VPWR is the desired turnon voltage

•

VHYS is the desired UVLO hysteresis at VPWR

(10)

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