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LM5035 Datasheet(PDF) 3 Page - Texas Instruments |
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LM5035 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 40 page  CS NC AGND RT COMP OVP SS HO LO PGND VCC SR1 SR2 REF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 EP RAMP CS AGND RT COMP OVP UVLO RES DLY SS HB HS HO LO PGND VCC SR2 SR1 REF VIN 1 2 3 4 5 6 7 13 14 15 16 17 18 19 8 9 10 12 11 20 EP 13 LM5035 www.ti.com SNVS428H – JANUARY 2006 – REVISED OCTOBER 2015 5 Pin Configuration and Functions PWP Package NHZ Package 20-Pin HTSSOP With PowerPAD 24-Pin WQFN Top View Top View Pin Functions PIN NO. TYPE DESCRIPTION APPLICATION INFORMATION NAME HTSSOP WQFN AGND 6 5 GND Analog ground Connect directly to Power Ground. An external optocoupler connected to the COMP pin sources current into an internal NPN current mirror. The PWM duty cycle is maximum with zero input COMP 4 3 I/O Input to the pulse width modulator current, while 1mA reduces the duty cycle to zero. The current mirror improves the frequency response by reducing the AC voltage across the optocoupler detector. If CS exceeds 0.25 V, the output pulse will be terminated, entering cycle-by- CS 7 6 I Current sense input for current limit cycle current limit. An internal switch holds CS low for 50 ns after HO or LO switches high to blank leading edge transients. Timing programming pin for the LO and HO An external resistor to ground sets the timing for the nonoverlap time of HO to DLY 9 8 I to SR1 and SR2 outputs SR1 and LO to SR2. An external diode is required from VCC to HB and an external capacitor is HB 11 11 I/O Boost voltage for the HO driver required from HS to HB to power the HO gate driver. HO 13 13 O High side gate drive output Output of the high side PWM gate driver. Capable of sinking 2-A peak current. Connection common to the transformer and both power switches. Provides a HS 12 12 I/O Switch node return path for the HO gate driver. LO 14 14 O Low side gate drive output Output of the low side PWM gate driver. Capable of sinking 2-A peak current. NC 1, 10, 20, 22 — No connection No electrical contact. An external voltage divider from the power source sets the shutdown levels. OVP 3 2 I Line overvoltage protection The threshold is 1.25 V. Hysteresis is set by an internal current source that sources 23 µA into the external resistor divider. PGND 15 15 GND Power ground Connect directly to Analog Ground. An external RC circuit from VIN sets the ramp slope. This pin is discharged at RAMP 1 23 I Modulator ramp signal the conclusion of every cycle by an internal FET. Discharge is initiated by either the internal clock or the Volt Second clamp comparator. REF 19 19 O Output of 5-V reference Maximum output current is 20 mA. Locally decoupled with a 0.1-µF capacitor. Normally biased at 2 V. An external resistor connected between RT and AGND Oscillator frequency control and sync clock sets the internal oscillator frequency. The internal oscillator can be RT 5 4 I input synchronized to an external clock with a frequency higher than the free running frequency set by the RT resistor. Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM5035 |
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