LM5035

SNVS428H – JANUARY 2006 – REVISED OCTOBER 2015

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Pin Functions (continued)

PIN

NO.

TYPE

DESCRIPTION

APPLICATION INFORMATION

NAME

HTSSOP

WQFN

If cycle-by-cycle current limit is exceeded during any cycle, a 22-µA current is

sourced to the RES pin capacitor. If the RES capacitor voltage reaches 2.5 V,

RES

10

9

I

Restart timer

the soft-start capacitor will be fully discharged and then released with a pull-up

current of 1.2 µA. After the first output pulse at LO (when SS > COMP offset,

typically 1 V), the SS pin charging current will revert to 55 µA.

SR1

18

18

O

Synchronous rectifier driver output

Control output of the synchronous FET gate. Capable of 0.5-A peak current.

SR2

17

17

O

Synchronous rectifier driver output

Control output of the synchronous FET gate. Capable of 0.5-A peak current.

An internal 55-µA current source charges an external capacitor to set the soft-

SS

8

7

I

Soft-start input

start rate. During a current limit restart sequence, the internal current source is

reduced to 1.2 µA to increase the delay before retry.

An external voltage divider from the power source sets the shutdown and

standby comparator levels. When UVLO reaches the 0.4-V threshold the VCC

UVLO

2

24

I

Line undervoltage lockout

and REF regulators are enabled. When UVLO reaches the 1.25-V threshold,

the SS pin is released and the device enters the active mode. Hysteresis is set

by an internal current sink that pulls 23 µA from the external resistor divider.

If an auxiliary winding raises the voltage on this pin above the regulation set-

Output of the high voltage start-up regulator.

VCC

16

16

I/O

point, the start-up regulator will shutdown, thus reducing the internal power

The VCC voltage is regulated to 7.6 V

dissipation.

Input to the Start-up Regulator. Operating input range is 13 V to 100 V with

VIN

20

21

I

Input voltage source

transient capability to 105 V. For power sources outside of this range, the

LM5035 can be biased directly at VCC by an external regulator.

Exposed pad, underside of package (WQFN)

No electrical contact. Connect to system ground plane for reduced thermal

EP

GND

resistance.

PowerPAD (HTSSOP)

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1) (2)

MIN

MAX

UNIT

VIN to GND

–0.3

105

V

HS to GND

–1

105

V

HB to GND

–0.3

118

V

HB to HS

–0.3

18

V

VCC to GND

–0.3

16

V

CS, RT, DLY to GND

–0.3

5.5

V

COMP input current

10

mA

All other inputs to GND

–0.3

7

V

Junction temperature

150

°C

Storage temperature, Tstg

–65

150

°C

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office or Distributors for availability and

specifications.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(2)

±1500

Electrostatic

V(ESD)

(1)

V

Charged-device model (CDM), per JEDEC specification JESD22-

discharge

±1000

C101(3)

(1)

The human body model is a 100-pF capacitor discharged through a 1.5-k

Ω resistor into each pin. 2 kV for all pins except HB, HO, and

HS, which are rated at 1.5 kV.

(2)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(3)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4

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