13

LM5025A

www.ti.com

SNVS293F – DECEMBER 2004 – REVISED AUGUST 2016

Product Folder Links: LM5025A

Submit Documentation Feedback

Copyright © 2004–2016, Texas Instruments Incorporated

7.3 Feature Description

7.3.1 High-Voltage Start-Up Regulator

The LM5025A contains an internal high-voltage start-up regulator that allows the input pin (VIN) to be connected

directly to the line voltage. The regulator output is internally current-limited to 20 mA. When power is applied, the

regulator is enabled and sources current into an external capacitor connected to the VCC pin. The recommended

capacitance range for the VCC regulator is 0.1 µF to 100 µF. When the voltage on the VCC pin reaches the

regulation point of 7.6 V and the internal voltage reference (REF) reaches its regulation point of 5 V, the

controller outputs are enabled. The outputs remain enabled until VCC falls below 6.2 V or the line undervoltage

lockout detector indicates that VIN is out of range. In typical applications, an auxiliary transformer winding is

connected through a diode to the VCC pin. This winding must raise the VCC voltage above 8 V to shut off the

internal start-up regulator. Powering VCC from an auxiliary winding improves efficiency while reducing the

controller power dissipation.

When the converter auxiliary winding is inactive, external current draw on the VCC line must be limited so the

power dissipated in the start-up regulator does not exceed the maximum power dissipation of the controller.

An external start-up regulator or other bias rail can be used instead of the internal start-up regulator by

connecting the VCC and the VIN pins together and feeding the external bias voltage into the two pins.

7.3.2 Line Undervoltage Detector

The LM5025A contains a line undervoltage lockout (UVLO) circuit. An external setpoint voltage divider from VIN

to GND, sets the operational range of the converter. The divider must be designed such that the voltage at the

UVLO pin is greater than 2.5 V when VIN is in the desired operating range. If the undervoltage threshold is not

met, both outputs are disabled, all other functions of the controller remain active. UVLO hysteresis is

accomplished with an internal 20-µA current source that is switched ON or OFF into the impedance of the

setpoint divider. When the UVLO threshold is exceeded, the current source is activated to instantly raise the

voltage at the UVLO pin. When the UVLO pin voltage falls below the 2.5-V threshold, the current source is turned

off, causing the voltage at the UVLO pin to fall. The UVLO pin can also be used to implement a remote enable

and disable function. Pulling the UVLO pin below the 2.5-V threshold disables the PWM outputs.

7.3.3 PWM Outputs

The relative phase of the main (OUT_A) and active clamp outputs (OUT_B) can be configured for the specific

application. For active clamp configurations using a ground-referenced P-channel clamp switch, the two outputs

must be in-phase with the active clamp output overlapping the main output. For active clamp configurations using

a high-side N-channel switch, the active clamp output must be out-of-phase with main output, and there must be

a dead time between the two gate drive pulses. A distinguishing feature of the LM5025A is the ability to

accurately configure either dead time (both OFF) or overlap time (both ON) of the gate driver outputs. The

overlap and dead-time magnitude is controlled by the resistor value connected to the TIME pin of the controller.

The opposite end of the resistor can be connected to either REF for dead-time control or GND for overlap

control. The internal configuration detector senses the connection and configures the phase relationship of the

main and active clamp outputs. The magnitude of the overlap and dead time can be calculated in Equation 1 and

Equation 2.

Overlap Time (ns) = 2.8 × RSET – 1.2

(1)

Dead Time (ns) = 2.9 × RSET +20

where

•

RSET in kΩ

•

Time in ns

(2)