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LM2743MTC/NOPB Datasheet(PDF) 23 Page - Texas Instruments |
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LM2743MTC/NOPB Datasheet(HTML) 23 Page - Texas Instruments |
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23 / 44 page ![]() = 4.5 kHz RO + RL fDP = 1 2S LCO(RO + ESR) VIN ADC = VRAMP = 3.3 1.0 = 10.4 dB + - + VRAMP + - VREF + - 10 k: 10 k: CC1 CC2 RC1 RC2 CC3 L RL CO RO VIN RC + - 23 LM2743 www.ti.com SNVS276I – APRIL 2004 – REVISED FEBRUARY 2019 Product Folder Links: LM2743 Submit Documentation Feedback Copyright © 2004–2019, Texas Instruments Incorporated Typical Applications (continued) D1 - A small Schottky diode should be used for the bootstrap. It allows for a minimum drop for both high and low- side drivers. The MBR0520 or BAT54 work well in most designs. RCS - Resistor used to set the current limit. Since the design calls for a peak current magnitude (IOUT+ (0.5 x ΔIOUT)) of 4.8 A, a safe setting would be 6A. (This is below the saturation current of the output inductor, which is 7 A.) Following the equation from the Current Limit section, a 1.3-k Ω resistor should be used. RFADJ - This resistor is used to set the switching frequency of the chip. The resistor value is calculated from equation in Normal Operation section. For 300-kHz operation, a 97.6-k Ω resistor should be used. CSS - The soft-start capacitor depends on the user requirements and is calculated based on the equation given in the section titled Start Up and Soft-Start. Therefore, for a 700-μs delay, a 12-nF capacitor is suitable. 8.2.1.2.8 Control Loop Compensation The LM2743 uses voltage-mode (‘VM’) PWM control to correct changes in output voltage due to line and load transients. One of the attractive advantages of voltage mode control is its relative immunity to noise and layout. However VM requires careful small signal compensation of the control loop for achieving high bandwidth and good phase margin. The control loop is comprised of two parts. The first is the power stage, which consists of the duty cycle modulator, output inductor, output capacitor, and load. The second part is the error amplifier, which for the LM2743 is a 9-MHz op-amp used in the classic inverting configuration. Figure 32 shows the regulator and control loop components. Figure 32. Power Stage and Error Amplifier One popular method for selecting the compensation components is to create Bode plots of gain and phase for the power stage and error amplifier. Combined, they make the overall bandwidth and phase margin of the regulator easy to see. Software tools such as Excel, MathCAD, and Matlab are useful for showing how changes in compensation or the power stage affect system gain and phase. The power stage modulator provides a DC gain ADC that is equal to the input voltage divided by the peak-to-peak value of the PWM ramp. This ramp is 1.0VP-P for the LM2743. The inductor and output capacitor create a double pole at frequency fDP, and the capacitor ESR and capacitance create a single zero at frequency fESR. For this example, with VIN = 3.3 V, these quantities are: (30) (31) |
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