LM2743MTCSLASHNOPB datasheet(10/44 Pages) TI2

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CSS =

tSS

PWM

ILIM

40 PA

10 PA

SYNCHRONOUS

DRIVER LOGIC

10 Ps

DELAY

0.71V

0.434V

SHUT DOWN

LOGIC

UVLO

VCC

SGND

EAO

BOOT

ISEN

PWGD

SS/TRACK

PGND

90 PA

SSDONE

Soft-Start

Comparator

+ Logic

VREF = 0.6V

REF

PWM LOGIC

CLOCK &

RAMP

FREQ

PGND

1VPP

LM2743

SNVS276I – APRIL 2004 – REVISED FEBRUARY 2019

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7 Detailed Description

7.1 Overview

The LM2743 is a voltage-mode, high-speed synchronous buck regulator with a PWM control scheme. It has

output shutdown (SD), input under-voltage lock-out (UVLO) mode and power good (PWGD) flag (based on over-

voltage and under-voltage detection). The over-voltage and under-voltage signals are logically OR'ed to drive the

power good signal and provide a logic signal to the system if the output voltage goes out of regulation. Current

limit is achieved by sensing the voltage VDS across the low-side MOSFET.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Start Up and Soft-Start

When VCC exceeds 2.76V and the shutdown pin (SD) sees a logic high, the soft-start period begins. Then an

internal, fixed 10 µA source begins charging the soft-start capacitor. During soft-start the voltage on the soft-start

capacitor CSS is connected internally to the non-inverting input of the error amplifier. The soft-start period lasts

until the voltage on the soft-start capacitor exceeds the LM2743 reference voltage of 0.6V. At this point the

reference voltage takes over at the non-inverting error amplifier input. The capacitance of CSS determines the

length of the soft-start period, and can be approximated by:

where

LM2743MTC/NOPB Datasheet(PDF) 10 Page - Texas Instruments

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