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AFE5804 Datasheet(PDF) 12 Page - Texas Instruments |
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AFE5804 Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 82 page  12 ADS5294 SLAS776E – NOVEMBER 2011 – REVISED APRIL 2018 www.ti.com Product Folder Links: ADS5294 Submit Documentation Feedback Copyright © 2011–2018, Texas Instruments Incorporated Electrical Characteristics Dynamic Performance (continued) Typical values are at 25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, –1 dBFS differential analog input, Sample rate = 80 MSPS, ADC is configured in internal reference mode (unless otherwise noted). MIN and MAX values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 1.8 V, LVDD = 1.8 V. PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT (1) The maximum limit used for the LVDD current at –40°C is 132 mA. DC ACCURACY Offset error Across devices and across channels within a device –15 15 mV Temperature coefficient of offset error < 0.01 mV/ °C E(GREF) Gain error due to internal reference inaccuracy alone Across devices –2 2 %FS E(GCHAN) Gain error of channel alone 0.5 %FS Temperature coefficient of E(GCHAN) < 0.01 %FS/ °C POWER SUPPLY Power consumption 80 MSPS, 14 Bit, 2-wire LVDS 77 mW/CH 50 MSPS, 1 wire LVDS 58 mW/CH 40 MSPS, 14 Bit, 1-wire LVDS 52 mW/CH 10 MSPS, 14 Bit, 1-wire LVDS 33 mW/CH fin = 10 MHz, 80 MSPS, 14 Bit, Decimation filter = 2, 1-wire LVDS 100 mW/CH AVDD 14 Bit, 80 MSPS 230 265 mA 14 Bit, 65 MSPS 200 mA 14 Bit, 40 MSPS 155 mA LVDD 80 MSPS, 14 Bit, 2-wire LVDS(1) 111 122 mA 50 MSPS, 14 Bit, 1-wire LVDS 80 mA 40 MSPS, 14 Bit, 1-wire LVDS 73 mA 80 MSPS, 1 Bit, Decimation filter = 2, 1-wire LVDS 210 mA Power-down power consumption Partial Power Down (80 MSPS, 2-wire) 175 mW Complete Power Down 60 mW Power supply modulation ratio Carrier = 5 MHz, f(PSRR) = 10 kHz, 50 mVpp on AVDD 35 dB Power supply rejection ratio AC power supply rejection ratio f = 10 kHz 55 dB 8.6 Digital Characteristics The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. AVDD = 1.8 V, LVDD = 1.8 V PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS/OUTPUTS VIH Logic high input voltage All digital inputs support 1.8-V and 3.3-V CMOS logic levels. 1.3 V VIL Logic low input voltage 0.4 V IIH Logic high input current VHIGH = 1.8 V 6 µA IIL Logic low input current VLOW = 0 V < 0.1 µA VOH Logic high output voltage AVDD - 0.1 V VOL Logic low output voltage 0.2 V LVDS OUTPUTS (see Figure 2) VODH High-level output differential voltage 100-Ω external termination 245 350 405 mV VODL Low-level output differential voltage 100-Ω external termination –245 –350 –405 mV VOCM Output common-mode voltage 900 1100 1300 mV |
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