AFE5804 datasheet(13/82 Pages) TI2

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ADS5294

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SLAS776E – NOVEMBER 2011 – REVISED APRIL 2018

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(1)

Timing parameters are ensured by design and characterization and not tested in production.

(2)

Measurements are done with a transmission line of 100-Ω characteristic impedance between the device and the load. Set-up and hold

time specifications take into account the effect of jitter on the output data and clock.

(3)

Data valid refers to logic HIGH of 100 mV and logic LOW of –100 mV.

8.7 Timing Requirements

Typical values are at 25°C, AVDD = 1.8 V, LVDD = 1.8 V, sampling frequency = 80 MSPS, 14-bit, sine wave input clock = 1.5

Vpp clock amplitude, CLOAD = 5 pF, RLOAD = 100 Ω, unless otherwise noted. MIN and MAX values are across the full

temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 1.8 V, LVDD = 1.7 V to 1.9 V

(1) (2) (3)

MIN

TYP

MAX

UNIT

Aperture delay

The delay in time between the rising edge of the input

sampling clock and the actual time at which the sampling

occurs

Aperture delay variation

Across channels within the same device

±175

Across devices at the same temperature and LVDD supply

2.5

Aperture jitter RMS

320

fs rms

Data latency

1-wire LVDS output interface

Clock

cycles

2-wire LVDS output interface

Clock

cycles

tSU

Data set-up time

80 MSPS, 2-wire LVDS, 7x-serialization

0.34

0.57

Data hold time

80 MSPS, 2-wire LVDS, 7x-serialization

0.55

0.8

tPROP

Clock propagation delay

Input clock rising edge (zero cross) to frame clock rising

edge (zero cross)

See LVDS Timing at Different

Sampling Frequencies — 2-Wire

Interface, 7x-Serialization, Digital

Filter Disabled and LVDS Timing at

Different Sampling Frequencies —

1-Wire Interface, 14x-Serialization,

Digital Filter Disabled

Variation of tPROP

Between two devices at same temperature and LVDD supply

±0.75

LVDS bit clock duty cycle

48%

tRISE

Data rise time

Rise time is from –100 mV to + 100 mV, 10

≤ Fs ≤ 80 MSPS

0.24

tFALL

Data fall time

Fall time is from +100 mV to –100 mV, 10

≤ Fs ≤ 80 MSPS

0.24

tCLKRISE

Output clock rise time

Rise time is from –100 mV to +100 mV, 10

≤ Fs ≤ 80 MSPS

0.20

tCLKFALL

Output clock fall time

Fall time is from +100 mV to –100 mV, 10

≤ Fs ≤ 80 MSPS

0.20

tWAKE

Wake-up Time

Time to valid data after coming out of COMPLETE POWER-

DOWN mode

100

µs

Time to valid data after coming out of PARTIAL POWER-

DOWN mode (with clock continuing to run during power-

down)

µs

AFE5804 Datasheet(PDF) 13 Page - Texas Instruments

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