DS501-00070-2v1-E

5

MB85R8M2TA



BLOCK DIAGRAM



FUNCTIONAL TRUTH TABLE

Operation Mode

/CE

/WE

/OE

A0 to A1 A2 to A18

/ZZ

/UB,/LB

Sleep

×

×

×

×

×

L

×

Standby

H

×

×

×

×

H

×

Read

↓

H

L

H or L

H or L

H

×

Address Access Read

L

H

L

H or L

↑ or ↓

H

×

Write(/CE Control)*1

↓

L

×

H or L

H or L

H

×

Write(/WE Control)*1*2

L

↓

×

H or L

H or L

H

×

Address Access Write*1*3

L

↓

×

H or L

↑ or ↓

H

×

Pre-charge

↑

×

×

×

×

H

×

Page Read

L

H

L

↑ or ↓

H or L

H

L

/UB,/LB Access Wright

L

L

H

H or L

H or L

H

↓

Page Address Write

L

↓

H

↑ or ↓

H or L

H

L

Note: H= “H” level,

L= “L” level,

↑= Rising edge,

↓= Falling edge,

×= H, L, ↓ or ↑

*1: In writing cycle, input data is latched at early rising edge of /CE or /WE.

*2: In writing sequence of /WE control, there exists time with data output of reading cycle at the falling

edge of /CE.

*3: In writing sequence of Address Access Write, there exists time with data output of reading cycle at the

address transition.

FeRAM Array

524,288×16

Column Decoder / Sense Amp.

/ Write Amp.

A0 to A18

/CE

/WE

/OE

/LB

/UB

/ZZ*

Address

I/O0 to I/O15

*equipped with FBGA only.