L9396 datasheet(81/109 Pages) STMICROELECTRONICS

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DS12539 Rev 10

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L9396

System functional safety implementations

109

WD Counter Setup

SPI parameters are programmable only before the WD mechanism starts. After the first

seed request, these parameters can be only read.

A WD1_RESET event does not clear programmed parameters; default values are applied

only as a consequence of a WSM_RESET.

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Addr

CRC

SPI parameter

Size

(bits)

default

Description

WD_RST_ EN

Enable for the WD_RST signal.

0: WD_RST signal not sent

1: WD_RST signal sent in case of failure

WD_REQ_CHECK_EN

Enable for the Request timing checking.

0: Request timing check not performed

1: Request timing check performed

WD_TO_RST_EN

Enable for the RST after Timeout generation.

0: RST not generated after a TO event

1: RST generated after a TO event

WD_CLK_DIV

Frequency Clock division setup.

0: clock not divided (64 µs)

1: clock divided by (256 µs)

WD_Th_Low

Threshold level to inhibit the drivers. If WD_CNT is lower than

the threshold no drivers are activated.

WD_Th_Low must be lower than WD_Th_High and minimum

WD_Th_High

Threshold level to start the actuation. If WD_CNT is lower than

the threshold actuation will be performed depending on the

previous state as shown in Figure 18.

WD_Th_High must be higher than WD_Th_Low.

WD_cnt_good_step

Number of incremental steps for WD_CNT as consequence of

a good event

WD_cnt_bad_step

Number of incremental steps for WD_CNT as consequence of

an error

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