STA369BW datasheet(82/89 Pages) STMICROELECTRONICS

Part #	STA369BW

Description	2.1-channel high-efficiency digital audio system Sound Terminal

PDF	89 Pages

Scroll/Zoom	100%

Manufacturer	STMICROELECTRONICS [STMicroelectronics]

Direct Link	http://www.st.com

Logo

82 / 89 page

STA369BW

82/89

DocID022033 Rev 2

8.24.4

Channel PWM enable (CPWMEN) bit (address 0x4B, bit D2)

This bit, when set, activates a mute output in case the volume reaches a value lower than

-76 dBFS.

8.24.5

Power-down delay selector (PNDLSL[2:0]) bits (address 0x4C, bit D4,

D3, D2)

As per Section 8.24.3, the assertion of PWDN activates a counter that, by default, after 13

million clock cycles puts the power bridge in tristate mode, independently from the fadeout

time. Using these registers it is possible to program this counter according to the following

table:

PNDLSL[2]

PNDLSL[1]

PNDLSL[2]

Fade out time

Default time (13M clock cycles)

Default time divided by 2

Default time divided by 4

Default time divided by 8

Default time divided by 16

Default time divided by 32

Default time divided by 64

Default time divided by 128

STA369BW Datasheet(PDF) 82 Page - STMicroelectronics