8.3.3.1 Connecting VPROPI Output to ADC

The analog output VPROPI varies proportionally with the SENSE voltage according to Equation 1. It’s important

to note even if VSENSE is negative VPROPI will remain at 0 V.

SENSE

VPROPI

5

V

u

(1)

An RC network in series with the VPROPI output is recommended, if this voltage is to be sampled by an analog

to digital converter.

Figure 8-3. RC Network in Series With the VPROPI Output

It is imperative to realize that VPROPI will decrease to 0 V while the H-Bridge enters slow decay recirculation.

8.3.4 Charge Pump

The charge pump is used to generate a supply above VBB to drive the source-side DMOS gates. A 0.1-μF

ceramic monolithic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.1-μF

ceramic monolithic capacitor, CStorage, should be connected between VCP and VBB to act as a reservoir to run

the high-side DMOS devices. The VCP voltage level is internally monitored and, in the case of a fault condition,

the outputs of the device are disabled.

8.3.5 Shutdown

As a measure to protect the device, faults caused by very high junction temperatures or low voltage on VCP

disable the outputs of the device until the fault condition is removed. At power on, the UVLO circuit disables the

drivers.

8.3.6 Low-Power Mode

Control input nSLEEP is used to minimize power consumption when the DRV880x is not in use. A logic low on

the nSLEEP input disables much of the internal circuitry, including the internal voltage rails and charge pump. A

logic high on this input pin results in normal operation. When switching from low to high, the user should allow a

1-ms delay before applying PWM signals. This time is needed for the charge pump to stabilize.

8.3.7 Braking

The braking function is implemented by driving the device in slow-decay mode (MODE 1 pin is high) and

deasserting the enable to low. Because it is possible to drive current in both directions through the DMOS

switches, this configuration effectively shorts out the motor-generated BEMF as long as the ENABLE chop mode

is asserted. The maximum current can be approximated by VBEMF/RL. Care should be taken to ensure that the

maximum ratings of the device are not exceeded in worse-case braking situations – high-speed and high-inertia

loads.

8.3.8 Diagnostic Output

The nFAULT pin signals a problem with the chip via an open-drain output. A motor fault, undervoltage condition,

or TJ > 160°C drives the pin low. This output is not valid when nSLEEP puts the device into minimum power

dissipation mode (that is, nSLEEP is low). nFAULT stays asserted (nFAULT = L) until VBB reaches VBBNFR to

give the charge pump headroom to reach its undervoltage threshold. nFAULT is a status-only signal and does

DRV8800, DRV8801

SLVS855K – JULY 2008 – REVISED MARCH 2021

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