F280049CPMSR datasheet(7/271 Pages) TI2

7 / 271 page

4 Revision History

Changes from February 1, 2021 to January 9, 2023

Page

• This Revision History lists the changes from SPRS945F to SPRS945G. ...................................................1

• Global: Updated devices in data sheet header.................................................................................................. 1

• Global: Changed title of Technical Reference Manual to TMS320F28004x Real-Time Microcontrollers

Technical Reference Manual. Changed title of data sheet to TMS320F28004x Real-Time Microcontrollers.

Changed title of errata to TMS320F28004x Real-Time MCUs Silicon Errata.....................................................1

• Global: Updated description of ERRORSTS..................................................................................................... 1

• Section 1, Features: Added "UART-Compatible" to "Two Serial Communication Interfaces (SCIs) (pin-

bootable)" feature. Added "UART-Compatible" to "One Local Interconnect Network (LIN)" feature. Added

"Functional Safety-Compliant" feature. Added "Safety-related certification" feature.......................................... 1

• Section 3, Description: Updated section.............................................................................................................2

• Device Information: Updated table..................................................................................................................... 2

• Table 3-1, Functional Safety-Compliant Part Numbers: Added table................................................................. 2

• Figure 3-1, Functional Block Diagram: Added "Secure memories are shown in red" note.................................5

• Table 5-1, Device Comparison: Removed F280048, F280048C, F280040, and F280040C from table header.

Updated device numbers for Configurable Logic Block (CLB). Updated device numbers for InstaSPIN-FOC™.

Added ADC channels (from PGA). Changed "SDFM channels – Type 1" of 64-pin PM from 3 to 2. Changed

"SDFM channels – Type 1" of 56-pin RSH from 3 to 2. Added "(UART-compatible)" to "SCI – Type 0". Added

"(UART-compatible)" to "LIN – Type 1". Updated PACKAGE OPTIONS, TEMPERATURE, AND

QUALIFICATION section.................................................................................................................................... 9

• Section 5.1, Related Products: Updated section.............................................................................................. 11

• Table 6-1, Pin Attributes: Updated DESCRIPTION of GPIO22_VFBSW, GPIO23_VSW, and ERRORSTS.

Added "When DCDCEN = 1 the respective bits in AMSEL register are don't cares" footnote......................... 16

• Table 6-3, Digital Signals: Updated DESCRIPTION of ERRORSTS................................................................ 35

• Digital Signals by GPIO table: Updated DESCRIPTION of ERRORSTS......................................................... 42

• Section 7.1, Absolute Maximum Ratings: Changed description of Input clamp current from "Digital/analog

input (per pin)" to "Digital input (per pin)". ........................................................................................................57

• Section 7.2, ESD Ratings – Commercial: Updated device numbers. Added Charged-device model (CDM)

value for corner pins for 100-pin PZ package and 64-pin PM package............................................................57

• Section 7.3, ESD Ratings – Automotive: Updated device numbers................................................................. 58

• Section 7.4, Recommended Operating Conditions: Updated SRSUPPLY and its associated footnote...............58

• Section 7.6, Electrical Characteristics: Moved "150" from TYP column to MIN column for VHYSTERESIS......... 66

• Power Management Module (PMM) section: Updated section.........................................................................70

• Figure 7-12, Reset Circuit: Updated figure....................................................................................................... 81

• Figure 7-13, Power-on Reset: Added tboot-flash to "CPU Execution Phase" waveform......................................82

• Section 7.9.3, Clock Specifications: Removed Crystal Oscillator section. Added Crystal (XTAL) Oscillator

section.............................................................................................................................................................. 83

• Table 7-9, Minimum Required Flash Wait States (FRDCNTL[RWAIT]) at Different CPUCLK Frequencies:

Changed Minimum Required Flash Wait States with Different Clock Sources and Frequencies table to

Minimum Required Flash Wait States (FRDCNTL[RWAIT]) at Different CPUCLK Frequencies table. Updated

table.................................................................................................................................................................. 95

• Table 7-10, Flash Parameters: Changed "Nwec Write/Erase Cycles" to "Nwec Write/Erase Cycles per sector".

Added "Nwec Write/Erase Cycles for entire Flash (combined all sectors)" and associated footnote.................95

• Figure 7-26, Connecting to the 14-Pin JTAG Header: Changed TMS pullup resistance from 4.7 kΩ to 2.2 kΩ.

..........................................................................................................................................................................97

• Figure 7-27, Connecting to the 20-Pin JTAG Header: Changed TMS pullup resistance from 4.7 kΩ to 2.2 kΩ.

..........................................................................................................................................................................97

• Section 7.10.1.1, Result Register Mapping: Added section............................................................................120

• Section 7.10.1.3.3, ADC Input Model: Added references to the Charge-Sharing Driving Circuits for C2000

ADCs application report and the ADC Input Circuit Evaluation for C2000 MCUs application report..............124

• Section 7.10.2.1.2, PGA Characteristics: Added RFILT. Updated Bandwidth. Added "The DNL/INL of the PGA

is within the DNL/INL tolerance of the ADC and therefore not shown separately" footnote........................... 129

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TMS320F280049C-Q1, TMS320F280048C-Q1, TMS320F280041C-Q1, TMS320F280040C-Q1

TMS320F280049C, TMS320F280041C, TMS320F280049-Q1, TMS320F280048-Q1

TMS320F280041-Q1, TMS320F280040-Q1, TMS320F280049, TMS320F280045, TMS320F280041

SPRS945G – JANUARY 2017 – REVISED JANUARY 2023

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Product Folder Links: TMS320F280049C-Q1 TMS320F280048C-Q1 TMS320F280041C-Q1

TMS320F280040C-Q1 TMS320F280049C TMS320F280041C TMS320F280049-Q1 TMS320F280048-Q1

TMS320F280041-Q1 TMS320F280040-Q1 TMS320F280049 TMS320F280045 TMS320F280041

F280049CPMSR Datasheet(PDF) 7 Page - Texas Instruments

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