F280049CPMSR datasheet(72/271 Pages) TI2

72 / 271 page

7.9.1.2.3 Delay Blocks

The delay blocks in the path of the voltage monitors work together to delay the release time between the voltage

monitors and XRSn. These delays ensure that the voltages are stable when XRSn releases in external VREG

mode. The delay blocks are only active during power up (that is, when VDDIO and VDD are ramping up).

The delay blocks contribute to the minimum slew rates specified in Power Management Module Electrical Data

and Timing for the power rails.

Note

The delay numbers specified in the block diagram are typical numbers.

7.9.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)

The internal VREG is supplied by the VDDIO rail and can generate the 1.2 V required to power the VDD pins.

It is enabled by tying the VREGENZ pin low. Although the internal VREG eliminates the need to use an external

supply for VDD, decoupling capacitors are still required on the VDD pins for VREG stability and transients. See

VDD Decoupling for details.

7.9.1.2.5 VREGENZ

The VREGENZ (VREG disable) pin controls the state of the internal VREG. To enable the internal VREG,

the VREGENZ pin should be tied low. For applications supplying VDD externally (external VREG), the internal

VREG should be disabled by tying the VREGENZ pin high.

Note

Not all device packages have VREGENZ pinned out. For packages without VREGENZ, external

VREG mode is not supported.

7.9.1.2.6 Internal 1.2-V Switching Regulator (DC-DC)

The internal DC-DC regulator offers increased efficiency over the LDO for converting 3.3 V to 1.2 V. The internal

DC-DC regulator is supplied by the VDDIO_SW pin and generates the 1.2 V required to power the VDD pins. To

use the internal switching regulator, the core domain must power up initially using the internal LDO VREG supply

(tie the VREGENZ pin low to VSS) and then transition to the DC-DC regulator through application software

by setting the DCDCEN bit in the DCDCCTL register. VREGENZ must still be kept low after transition since

it controls both the DC-DC and LDO. Tying VREGENZ high disables both the DC-DC and LDO. The DC-DC

regulator also requires external components (inductor, input capacitance, and output capacitance). The output

of internal DC-DC regulator is not internally fed to the VDD rail and requires an external connection. Figure 7-8

shows the schematic implementation.

CVDDIO_SW

VDDIO_SW

VSS_SW

VSW

VFBSW

VIN

VDD

VSS_SW

CVDD_DECAP

(A)

VSS

VSS_SW

VSS

CVDD

VSS

F28004x

LVSW

VDD

One decoupling capacitor per each of the four VDD pins

Figure 7-8. DC-DC Circuit Schematic

The VDDIO_SW supply pin (VIN) requires a 3.3-V level voltage. A total input capacitance (CVDDIO_SW) of 20 µF is

required on VDDIO_SW. Due to the capacitor specification requirements detailed in Table 7-2, two parallel 10-µF

capacitors in parallel is the recommended configuration. Decoupling capacitors of 100 nF should also be placed

on each VDD pin as close to the device as possible.

TMS320F280049C-Q1, TMS320F280048C-Q1, TMS320F280041C-Q1, TMS320F280040C-Q1

TMS320F280049C, TMS320F280041C, TMS320F280049-Q1, TMS320F280048-Q1

TMS320F280041-Q1, TMS320F280040-Q1, TMS320F280049, TMS320F280045, TMS320F280041

SPRS945G – JANUARY 2017 – REVISED JANUARY 2023

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TMS320F280041-Q1 TMS320F280040-Q1 TMS320F280049 TMS320F280045 TMS320F280041

F280049CPMSR Datasheet(PDF) 72 Page - Texas Instruments

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