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SPSB081 Datasheet(PDF) 85 Page - STMicroelectronics |
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SPSB081 Datasheet(HTML) 85 Page - STMicroelectronics |
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85 / 137 page  7 SPI registers 7.1 Global status byte (GSB) Table 65. Global status byte (GSB) Global status byte (GSB) Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 1 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) GSBN RSTB SPIE PLE FE DE GW FS Global status bit inverted Reset SPI error Physical layer error (CAN, LIN) Functional error Device error Global warning Fail safe Table 66. Global status byte (GSB) description Bit Name Description 31 GSBN Global status bit inverted The GSBN is a logically NOR combination of GSB bits 24 to bit 30(1) This bit can also be used as global status flag without starting a complete communication frame as it is present at SDO directly after pulling CSN low 0 = Error detected (1 or several GSB bits from 24 to 30 are set) 1 = No error detected (default after power on) 30 RSTB Reset The RSTB indicates a device reset and is set in case of the following events: SR1 (0x31) • VPOR • WDFAIL • V1UV (when UV is more than tUV1) • FORCED SLEEP TSD2/V1SC 0 = No reset signal has been generated (default) 1 = Reset signal has been generated RSTB is cleared by a read and clear command to all bits in status register 1 causing the reset event. 29 SPIE(2) SPI error bit The SPIE indicates errors related to a wrong SPI communication SR7 (0x7) • SPI_INV_CMD • SPI_SCK_CNT The bit is also set in case of an SPI CSN time-out detection 0 = No error (default) 1 = Error detected 28 PLE(2) Physical layer error The PLE is a logical OR combination of errors related to the LIN and CAN transceivers SR2 (0x32) and SR6 (0x36) • LIN_PERM_DOM SPSB081 SPI registers DS14048 - Rev 3 page 85/137 |
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