ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC

SLLSE83F – APRIL 2013 – REVISED JANUARY 2015

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6.10 Switching Characteristics: VCC1 and VCC2 at 3.3 V ±10%

VCC1 and VCC2 at 3.3 V ±10% (over recommended operating conditions unless otherwise noted.)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tPLH, tPHL

Propagation delay time

15

23

45

See Figure 10

ns

PWD(1)

Pulse width distortion |tPHL – tPLH|

3

Same-direction Channels

2

tsk(o)

(2)

Channel-to-channel output skew time

ns

Opposite-direction

4

Channels

tsk(pp)

(3)

Part-to-part skew time

19

ns

tr

Output signal rise time

2.5

ns

See Figure 10

tf

Output signal fall time

2.5

ns

Disable propagation delay, from high/low to

tPHZ, tPLZ

6.5

15

ns

high-impedance output

See Figure 11

Enable propagation delay, from high-

tPZH, tPZL

6.5

15

ns

impedance to high/low output

Fail-safe output delay time from input data or

tfs

See Figure 12

8

μs

power loss

tGR

Input glitch rejection time

12.5

ns

(1)

Also known as pulse skew

(2)

tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same

direction while driving identical loads.

(3)

tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same

direction while operating at identical supply voltages, temperature, input signals and loads.

6.11 Switching Characteristics: VCC1 and VCC2 at 2.7 V

VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted.)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tPLH, tPHL

Propagation delay time

15

27

50

See Figure 10

ns

PWD(1)

Pulse width distortion |tPHL – tPLH|

3

Same-direction Channels

2

tsk(o)

(2)

Channel-to-channel output skew time

ns

Opposite-direction

4

Channels

tsk(pp)

(3)

Part-to-part skew time

22

ns

tr

Output signal rise time

3

ns

See Figure 10

tf

Output signal fall time

3

ns

Disable propagation delay, from high/low to high-

tPHZ, tPLZ

9

15

ns

impedance output

See Figure 11

Enable propagation delay, from high-impedance to

tPZH, tPZL

9

15

ns

high/low output

tfs

Fail-safe output delay time from input data or power loss

See Figure 12

8.5

μs

tGR

Input glitch rejection time

14

ns

(1)

Also known as pulse skew

(2)

tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same

direction while driving identical loads.

(3)

tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same

direction while operating at identical supply voltages, temperature, input signals, and loads.

8

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