MP9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER

When the HS-FET is on, VIN is about equal to

SW, so the bootstrap capacitor cannot be

charged.

At a higher duty cycle operation condition, the

time period available to the bootstrap charging

is less, so the bootstrap capacitor may not be

charged sufficiently. In case the external circuit

does not have sufficient voltage or time to

charge the bootstrap capacitor, extra external

circuitry can be used to ensure that the

bootstrap voltage is in the normal operation

region.

Low Dropout Operation (BST Refresh)

To improve dropout, the MP9840 is designed to

operate at close to 100% duty cycle for as long

as the BST to SW voltage is greater than 2.5V.

When the voltage from BST to SW drops below

2.5V, the HS-FET is turned off using an under-

voltage lockout (UVLO) circuit, which allows the

LS-FET to conduct and refresh the charge on

the BST capacitor. In DCM or PSM, the LS-FET

is forced on to refresh the BST voltage.

Since the supply current sourced from the BST

capacitor is low, the HS-FET can remain on for

more switching cycles than are required to

refresh the capacitor, making the effective duty

cycle of the switching regulator high.

The effective duty cycle during the dropout of

the regulator is mainly influenced by the voltage

drops across the power MOSFET, inductor

resistance, low-side diode and printed circuit

board resistance.

Internal Regulator

Most of the internal circuitry is powered on by

the 2.6V internal regulator. This regulator takes

the VIN input and operates in the full VIN range.

When VIN is greater than 3V, the output of the

regulator is in full regulation. When VIN is lower

than 3V, the output degrades.

For better thermal performance, connect BIAS

to an external 5V source. VCC and the internal

circuit are powered by BIAS. Since there is an

internal diode between BIAS and the internal

circuit, float BIAS or connect BIAS to GND if it

is not being used.

Enable (EN) Control

EN is a digital control pin that turns the

regulator on and off by either the external logic

H/L signal or programming the VIN UVLO (see

Figure 3). When EN is pulled below its

threshold voltage, the MP9840 is put into the

lowest shutdown current mode. Forcing EN

above the EN threshold voltage turns the

MP9840 on. With a high enough VIN, the

MP9840 can be enabled and disabled by EN.

Do not float EN.

EN

VIN

REN1

REN2

Figure 3: Enable Divider Circuit

Programmable Frequency (FREQ)

The

MP9840

oscillating

frequency

is

programmed either by an external resistor

(RFREQ) from FREQ to ground or by a logic level

SYNC signal. The value of RFREQ can be

calculated with Equation (1):

)

(

170000

)

(

11

.

1

kHz

f

k

Ω

R

s

FREQ

=

(1)

The chip can be synchronized to an external

clock ranging from 350kHz up to 2.5MHz

through FREQ/SYNC.

SYNC and PHASE

The

internal

oscillator

frequency

can

be

synchronized to an external clock ranging from

350kHz up to 2.5MHz through SYNC. The

external clock should be at least 250kHz larger

than the RFREQ set frequency. Ensure that the

high amplitude of the SYNC clock is higher than

1.8V and the low amplitude is lower than 0.4V.

There is no pulse width requirement, but there

is always parasitic capacitance of the pad, so if

the pulse width is too short, a clear rising and

falling edge may not be seen due to the

parasitic capacitance. A pulse longer than

100ns

is

recommended

in

application.

MP9840 Rev. 1.01

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1/23/2018

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