Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

ICS8402AYILF Datasheet(PDF) 8 Page - Integrated Device Technology

Part # ICS8402AYILF
Description  350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
PDF  19 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS8402AYILF Datasheet(HTML) 8 Page - Integrated Device Technology

Back Button ICS8402AYILF Datasheet HTML 4Page - Integrated Device Technology ICS8402AYILF Datasheet HTML 5Page - Integrated Device Technology ICS8402AYILF Datasheet HTML 6Page - Integrated Device Technology ICS8402AYILF Datasheet HTML 7Page - Integrated Device Technology ICS8402AYILF Datasheet HTML 8Page - Integrated Device Technology ICS8402AYILF Datasheet HTML 9Page - Integrated Device Technology ICS8402AYILF Datasheet HTML 10Page - Integrated Device Technology ICS8402AYILF Datasheet HTML 11Page - Integrated Device Technology ICS8402AYILF Datasheet HTML 12Page - Integrated Device Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 8 / 19 page
background image
ICS8402I
350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
8
ICS8402AYI REV. A OCTOBER 16, 2007
Table 6. Crystal Characteristics
AC Electrical Characteristics
Table 7A. AC Characteristics, VDD = VDDO = 3.3V±5%, TA = -40°C to 85°C
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Mode of Oscillation
Fundamental
Frequency
12
40
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7pF
Parameter Symbol
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency
15.625
350
MHz
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1, 3
40
100
ps
tjit(per)
Period Jitter, RMS; NOTE 1
8
30
ps
tsk(o)
Output Skew; NOTE 2, 3
80
ps
tR / tF
Output Rise/Fall Time
20% to 80%
0.25
1.1
ns
tS
Setup Time
M, N to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
tH
Hold Time
M, N to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
odc
Output Duty Cycle
ƒ
≤ 300MHz
40
60
%
tLOCK
PLL Lock Time
1ms



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com