SRC4382IPFBT datasheet(30/85 Pages) TI2

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SY C

BLS

(input)

BLS

(output)

Block Start

(Frame 0startshere)

DIGITAL INTERFACE RECEIVER (DIR) OPERATION

PL 1

AE 3

Decoder

Pulse

Generator

PL 2

128f

256f

512f

Clock

Divider

Divide by

1,2, 4,or8

DataStream

De-M x

RX1+(pin1)

RX1

(pin2)

RX2+(pin3)

RX2

(pin4)

RX3+(pin5)

RX3

(pin6)

RX4+(pin7)

RX4

(pin8)

LOCK

(pin 11)

RXCKO

(pin 12)

RXCKO

BYPMUX[10

: ]

R MUX[

1:0]

RXCLK

MC K

RXCKI

RXCKOF[1:0]

Ch1

(Left)

Audio

Ch2

(Right)

Audio

Cha ne

Status

Channel

Status

User

Daa

User

Daa

UserAccess

(UA)Buffers

Receiver

Access

(RA)Buffers

DIT

ToSPI orI CHostInterface

Receiver

Sy c

Generator

RCV_SYNC

Errorand

StatusOutputs

ToDIT Buffer

andLine Driver

Reference

Clock

Source

DIT

SRC4382

SBFS030C – JANUARY 2006 – REVISED SEPTEMBER 2007

Figure 66. DIT Block Start Timing

The DIR performs AES3 decoding and clock recovery and provides the differential line receiver functions. The

lock range of the DIR includes frame/sampling rates from 20kHz to 216kHz. Figure 67 shows the functional block

diagram for the DIR.

Four differential line receivers are utilized for signal conditioning the encoded input data streams. The receivers

can be externally configured for either balanced or unbalanced cable interfaces, as well as interfacing with

CMOS logic level inputs from optical receivers or external logic circuitry. See Figure 68 for a simplified schematic

for the line receiver. External connections are discussed in the Receiver Input Interfacing section.

Figure 67. Digital Interface Receiver (DIR) Functional Block Diagram

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