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SRC4382IPFBT Datasheet(PDF) 39 Page - Texas Instruments |
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SRC4382IPFBT Datasheet(HTML) 39 Page - Texas Instruments |
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39 / 85 page  www.ti.com S A A A A A P Byte1 Slav Ad e dress wit R h /W=0 Byte2 Reg t is erAddressByte wit I h NC=1 Byte3 SlaveAddress withR/W=1 Byte4 Reg t is erData ByteN Reg t is erData ForAddress+N (c)RandomReadOp mentEnabled eration,Auto-Incre S=STARTC di on tion A=Ackn w dg o le e A =NotAckno ledge w R=Repeated TART S P=STOPCondii n t o Transferfrom ste Ma r to Slave Transferfrom aveto Sl Master L gend e R S A A P Byte1 SlaveAddre s s withR/W=1 Byte2 Reg t is erAddressByte withINC=0 (a Cu ) rrentAd res heRegister ddr ss fthe vio s d A e Pre u s Read,Assumest o S A A A P Byte1 Slav Ad e dress withR/W=0 Byte2 Reg t is erAddressByte withINC=0 Byte3 Slav Ad e dress withR/W=1 (b)RandomReadOp me tDisabled eration,Auto-Incre n R A Byte4 RegisterData INTERRUPT OUTPUT VIO 10k W Tothe outputsf INT or additionalSRC4382 devices Interrupt Logic SRC4382 MCU,DSP, orLogic INT 23 Interrupt Input SRC4382 SBFS030C – JANUARY 2006 – REVISED SEPTEMBER 2007 Figure 78. Fast/Standard Mode Read Operations The SRC4382 includes multiple internal status bits, many of which may be set to trigger an interrupt signal. The interrupt signal is output at INT (pin 23), which is an active low, open-drain output. The INT pin requires a pull-up resistor to the VIO supply rail. The value of the pull-up is not critical, but a 10k Ω device should be sufficient for most applications. Figure 79 shows the interrupt output pin connection. The open-drain output allows interrupt pins from multiple SRC4382 devices to be connected in a wired OR configuration. Figure 79. Interrupt Output Pin Connections Copyright © 2006–2007, Texas Instruments Incorporated Submit Documentation Feedback 39 Product Folder Link(s): SRC4382 |
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