SRC4382IPFBT datasheet(53/85 Pages) TI2

53 / 85 page

www.ti.com

SRC4382

SBFS030C – JANUARY 2006 – REVISED SEPTEMBER 2007

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

ACLK1

ACLK0

ADIV1

ADIV0

ADIV[1:0]

Port A Master Clock Divider

These bits are used to set the master clock divider for generating the LRCKA clock for Port A when configured for Master mode operation.

BCKA is always set to 64 times the LRCKA clock rate in Master mode.

ADIV1

ADIV0

Master Mode Clock Divider

Divide By 128 (Default)

Divide By 256

Divide By 384

Divide By 512

ACLK[1:0]

Port A Master Clock Source

These bits are used to set the master clock source for Port A when configured for Master mode operation.

ACLK1

ACLK0

Master Clock Source

MCLK (Default)

RXCKI

RXCKO

Reserved

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

BMUTE

BOUTS1

BOUTS0

BM/S

BFMT2

BFMT1

BFMT0

BFMT[2:0]

Port B Audio Data Format

These bits are used to set the audio input and output data format for Port B. Refer to the Audio Serial Port Operation section for

illustrations of the supported data formats. Refer to the Electrical Characteristics: Audio Serial Ports table and Figure 1 for an applicable

timing diagram and parameters.

BFMT2

BFMT1

BFMT0

Audio Data Format

24-Bit Left-Justified (Default)

24-Bit Philips I2S

Unused

16-Bit Right-Justified

18-Bit Right-Justified

20-Bit Right-Justified

24-Bit Right-Justified

Note: When the SRC is selected as the output data source for Port B and the data format for the port is set to Right-Justified, the proper

word length must be selected in the Port B control registers such that it matches the corresponding SRC output data word length. Refer to

control register 0x2F for the SRC output word length selection.

BM/S

Port B Slave/Master Mode

This bit is used to set the audio clock mode for Port B to either Slave or Master.

BM/S

Slave/Master Mode

Slave mode; the LRCK and BCK clocks are generated by an external source. (Default)

Master mode; the LRCK and BCK clocks are derived from the Port A master clock source.

BOUTS[1:0]

Port B Output Source

These bits are used to select the output data source for Port B. The data is output at SDOUTB (pin 45).

BOUTS1

BOUTS0

Output Data Source

Port B Input, for data loop back. (Default)

Port A Input

DIR

SRC

BMUTE

Port B Output Mute

Submit Documentation Feedback

Product Folder Link(s): SRC4382

SRC4382IPFBT Datasheet(PDF) 53 Page - Texas Instruments

SRC4382IPFBT Datasheet(HTML) 53 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85

Datasheet Download

Link URL