5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)

MIN

MAX

UNIT

AVDD to AVSS

–0.3

2.2

V

DVDD to DVSS

–0.3

2.2

V

SPKVDD to SPKVSS

–0.3

6

V

IOVDD to IOVSS

–0.3

3.9

V

Digital input voltage

IOVSS – 0.3

IOVDD + 0.3

V

Analog input voltage

AVSS – 0.3

AVDD + 0.3

V

Operating temperature

–40

85

°C

Junction temperature, TJ Max

105

°C

Power dissipation for VQFN package (with thermal pad soldered to board)

(TJ Max – TA) / θJA

W

Storage temperature, Tstg

–55

150

°C

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

5.2 ESD Ratings

VALUE

UNIT

V(ESD)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)

±500

V

Charged-device model (CDM), per JEDEC specification JESD22-C101(2)

±250

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

AVDD(2)

Power-supply voltage

Referenced to AVSS(1)

1.5

1.8

1.95

V

DVDD

Referenced to DVSS

(1)

1.65

1.8

1.95

SPKVDD(2)

Referenced to SPKVSS

(1)

2.7

5.5

IOVDD

Referenced to IOVSS

(1)

1.1

1.8

3.6

Speaker impedance

Load applied across class-D output pins (BTL)

4

Ω

VI

Analog audio full-scale input

voltage

AVDD = 1.8V, single-ended

0.5

VRMS

MCLK(3)

Master clock frequency

IOVDD = DVDD = 1.8V

50

MHz

SCL

SCL clock frequency

400

kHz

TA

Operating free-air temperature

–40

85

°C

(1)

All grounds on board are tied together, so they should not differ in voltage by more than 0.2 V maximum for any combination of ground

signals. By use of a wide trace or ground plane, ensure a low-impedance connection between AVSS and DVSS.

(2)

To minimize battery-current leakage, the SPKVDD voltage level should not be below the AVDD voltage level.

(3)

The maximum input frequency should be 50 MHz for any digital pin used as a general-purpose clock.

5.4 Thermal Information

THERMAL METRIC(1)

TAS2505

UNIT

RGE (QFN)

24 PINS

θJA

Junction-to-ambient thermal resistance

32.2

°C/W

θJCtop

Junction-to-case (top) thermal resistance

30

°C/W

TAS2505

SLAS778D – FEBRUARY 2013 – REVISED JANUARY 2025

www.ti.com

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