PC BOARD LAYOUT TECHNIQUES FOR

THS4504

THS4505

SLOS363D – AUGUST 2002 – REVISED MAY 2008 ......................................................................................................................................................... www.ti.com

add a pole and/or a zero below 400 MHz that can

OPTIMAL PERFORMANCE

effect circuit operation. Keep resistor values as

low as possible, consistent with load driving

Achieving

optimum

performance

with

a

high

considerations.

frequency amplifier-like devices in the THS4500

• Connections to other wideband devices on the

family requires careful attention to board layout

board may be made with short direct traces or

parasitic and external component types.

through onboard transmission lines. For short

Recommendations that optimize performance include:

connections, consider the trace and the input to

the next device as a lumped capacitive load.

• Minimize parasitic capacitance to any ac ground

Relatively wide traces (50 mils to 100 mils) should

for all of the signal I/O pins. Parasitic capacitance

be used, preferably with ground and power planes

on the output and input pins can cause instability.

opened up around them. Estimate the total

To reduce unwanted capacitance, a window

capacitive load and determine if isolation resistors

around the signal I/O pins should be opened in all

on the outputs are necessary. Low parasitic

of the ground and power planes around those

capacitive loads (< 4 pF) may not need an RS

pins. Otherwise, ground and power planes should

since

the

THS4500

family

is

nominally

be unbroken elsewhere on the board.

compensated to operate with a 2-pF parasitic

• Minimize the distance (< 0.25”) from the

load. Higher parasitic capacitive loads without an

power-supply

pins

to

high-frequency

0.1-

µF

RS are allowed as the signal gain increases

decoupling capacitors. At the device pins, the

(increasing the unloaded phase margin). If a long

ground and power-plane layout should not be in

trace is required, and the 6-dB signal loss intrinsic

close proximity to the signal I/O pins. Avoid

to

a

doubly-terminated

transmission

line

is

narrow power and ground traces to minimize

acceptable, implement a matched impedance

inductance between the pins and the decoupling

transmission line using microstrip or stripline

capacitors. The power-supply connections should

techniques (consult an ECL design handbook for

always

be

decoupled

with

these

capacitors.

microstrip and stripline layout techniques).

Larger (6.8

µF or more) tantalum decoupling

• A 50-Ω environment is normally not necessary

capacitors, effective at lower frequency, should

onboard,

and

in

fact,

a

higher

impedance

also be used on the main supply pins. These may

environment improves distortion as shown in the

be placed somewhat farther from the device and

distortion versus load plots. With a characteristic

may be shared among several devices in the

board trace impedance defined based on board

same area of the PC board. The primary goal is to

material and trace dimensions, a matching series

minimize

the

impedance

seen

in

the

resistor into the trace from the output of the

differential-current return paths.

THS4500 family is used as well as a terminating

• Careful selection and placement of external

shunt resistor at the input of the destination

components

preserve

the

high

frequency

device.

performance of the THS4500 family. Resistors

• Remember also that the terminating impedance is

should

be

a

very

low

reactance

type.

the parallel combination of the shunt resistor and

Surface-mount resistors work best and allow a

the input impedance of the destination device: this

tighter

overall

layout.

Metal-film

and

carbon

total effective impedance should be set to match

composition, axially-leaded resistors can also

the trace impedance. If the 6-dB attenuation of a

provide good high frequency performance. Again,

doubly

terminated

transmission

line

is

keep their leads and PC board trace length as

unacceptable,

a

long

trace

can

be

short as possible. Never use wirewound type

series-terminated at the source end only. Treat

resistors in a high-frequency application. Since the

the trace as a capacitive load in this case. This

output pin and inverting input pins are the most

does not preserve signal integrity as well as a

sensitive to parasitic capacitance, always position

doubly-terminated line. If the input impedance of

the feedback and series output resistors, if any, as

the destination device is low, there is some signal

close as possible to the inverting input pins and

attenuation due to the voltage divider formed by

output pins. Other network components, such as

the series output into the terminating impedance.

input termination resistors, should be placed close

to the gain-setting resistors. Even with a low

• Socketing a high speed part like the THS4500

parasitic

capacitance

shunting

the

external

family is not recommended. The additional lead

resistors, excessively high resistor values can

length and pin-to-pin capacitance introduced by

create significant time constants that can degrade

the socket can create an extremely troublesome

performance.

Good

axial

metal-film

or

parasitic network which can make it almost

surface-mount

resistors

have

approximately

impossible to achieve a smooth, stable frequency

0.2 pF in shunt with the resistor. For resistor

response. Best results are obtained by soldering

values > 2.0 k

Ω, this parasitic capacitance can

the THS4500 family parts directly onto the board.

28

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