TLV9101 datasheet(12/91 Pages) TI2

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6.7 Electrical Characteristics

For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VO UT

= VS / 2, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OFFSET VOLTAGE

VOS

Input offset voltage

VCM = V–

±0.3

±1.5

TA = –40°C to 125°C

±1.75

dVOS/dT

Input offset voltage drift

TA = –40°C to 125°C

±0.6

µV/

℃

PSRR

Input offset voltage versus

power supply

VCM = V–

TA = –40°C to 125°C

±0.1

±0.7

µV/V

Channel separation

f = 0 Hz

µV/V

INPUT BIAS CURRENT

Input bias current

±10

IOS

Input offset current

±5

NOISE

Input voltage noise

f = 0.1 Hz to 10 Hz

µVPP

µVRMS

Input voltage noise density

f = 1 kHz

nV/√Hz

f = 10 kHz

Input current noise

f = 1 kHz

fA/√Hz

INPUT VOLTAGE RANGE

VCM

Common-mode voltage range

(V–) – 0.2

(V+) + 0.2

CMRR

Common-mode rejection ratio

VS = 16 V, (V–) – 0.1 V < VCM <

(V+) – 2 V (Main input pair)

TA = –40°C to 125°C

110

VS = 4 V, (V–) – 0.1 V < VCM <

(V+) – 2 V (Main input pair)

VS = 2.7 – 16 V, (V+) – 1 V < VCM

< (V+) + 0.1 V (Aux input pair)

(V+) – 2 V < VCM < (V+) – 1 V

See Offset Voltage (Transition Region) in the Typical

Characteristics section

INPUT CAPACITANCE

ZID

Differential

100 || 3

MΩ || pF

ZICM

Common-mode

6 || 1

TΩ || pF

TLV9101, TLV9102, TLV9104

SBOS943E – FEBRUARY 2019 – REVISED AUGUST 2021

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