ADA4356ABCZ datasheet(42/61 Pages) AD

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Data Sheet

ADA4356

analog.com

Rev. 0

42 of 61

wide range of duty cycles with the DCS on. To disable the DCS function, clear the least significant bit of SPI REGISTER

0x09h to zero.

Jitter in the rising edge of the clock is still a concern and is not easily reduced by the internal stabilization circuit. The

duty cycle control loop does not function for clock rates <20MHz, nominally. The loop has a time constant associated

with it that must be considered in applications where the clock rate can change dynamically. A wait time of 5µs is

required after a dynamic clock frequency increase or decrease before the DCS loop relocks to the input signal.

Jitter Considerations

High-speed, high-resolution ADCs are sensitive to the quality of the clock input. The following equation shows how

signal-to-noise ratio (SNR) degrades at a given input frequency (fA) due only to aperture jitter (tJ):

SNR Degradation = 20 log

10 (

2π×fA×tJ

)

In this equation, the rms aperture jitter represents the rms of all jitter sources, including the clock input, analog

input signal, and ADC aperture jitter specifications. IF undersampling applications are particularly sensitive to jitter.

The effect of jitter alone on SNR, with no other noise contributors, is shown Figure 90.

Figure 90. Ideal SNR vs. Analog Input Frequency and Jitter

Treat the clock input as an analog signal when aperture jitter can affect the dynamic range of the ADA4356. Separate

clock driver power supplies from the ADC output driver supplies to avoid modulating the clock signal with digital

noise. Low jitter, crystal oscillators are the best clock sources. If the clock is generated from another type of source

(by gating, dividing, or other methods), it is recommended to retime the clock by the original clock as the last step.

For more details on jitter performance as it relates to the internal ADC of the ADA4356, refer to the Application Note

AN-501: Aperture Uncertainty and ADC System Performance and the Application Note AN-756: Sampled Systems and

the Effects of Clock Phase Noise and Jitter.

Clock Stability Considerations

Immediately after power-on, the ADA4356 enters an initialization phase during which an internal state machine sets

up the biases and the registers for proper operation. During the initialization process, the ADA4356 needs a stable

clock. If the clock source to the ADC is not present or not stable during ADC power-up, it disrupts the state machine

and causes the ADC to start up in an unknown state. To correct this, invoke a digital reset via Register 0x08 after the

clock source is stable. Clock instability during normal operation may also necessitate a digital reset to restore proper

operation.

100

ANALOG INPUT FREQUENCY (MHz)

1000

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RMS CLOCK JITTER REQUIREMENT

ADA4356ABCZ Datasheet(PDF) 42 Page - Analog Devices

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