TMP411CD datasheet(34/61 Pages) TI2

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The LTHRM bit reads as 1 if the local temperature exceeds the local THERM limit, remains greater than the local

THERM limit, and less than the value in the shared Hysteresis Register, as shown in Figure 7-8.

The LHIGH and RHIGH bit values depend on the state of the AL or TH bit in the Configuration Register. If the

AL or TH bit is 0, the LHIGH bit reads as 1 if the local high limit is exceeded since the last clearing of the Status

LHIGH reads as 1 if the local temperature has exceeded the local high limit and remains greater than the local

high limit, and less than the value in the Hysteresis Register.

The RHIGH bit reads as 1 if the remote temperature exceeds the remote high limit and remains greater than the

remote high limit, and less than the value in the Hysteresis Register.

The LLOW and RLOW bits are not effected by the AL or TH bit. The LLOW bit reads as 1 if the local low limit

is exceeded since the last clearing of the Status Register. The RLOW bit reads as 1 if the remote low limit is

exceeded since the last clearing of the Status Register. When there is no remote diode connected and the power

supply ramp rate is less than 240V/s, RLOW flag is set as well and must be ignored.

The values of the LLOW, RLOW, and OPEN (as well as LHIGH and RHIGH when AL or TH is 0) are latched

and are read as 1 until the Status Register is read or a device reset occurs. These bits are cleared by reading

the Status Register, provided that the condition causing the flag to be set no longer exists. The values of BUSY,

LTHRM, and RTHRM (as well as LHIGH and RHIGH when ALERT/THERM2 is 1) are not latched and are not

cleared by reading the Status Register. The values indicate the current state, and are updated appropriately at

the end of the corresponding ADC conversion. Clearing the Status Register bits does not clear the state of the

ALERT pin. An SMBus alert response address command must clear the ALERT pin.

The TMP411/TMP411D NORs LHIGH, LLOW, RHIGH, RLOW, and OPEN, so a status change for any of these

flags from 0 to 1 automatically causes the ALERT pin to go low. (This only applies when the ALERT/THERM2

pin is configured for ALERT mode).

Table 8-2. Status Register Format

STATUS REGISTER (READ = 02h, WRITE = NA)

Bit Number

Bit Name

BUSY

LHIGH

LLOW

RHIGH

RLOW

OPEN

RTHRM

LTHRM

POR Value

0 (1)

(1)

The BUSY bit changes to 1 almost immediately (<< 100µs) following power-up, as the TMP411/TMP411D device begins the first

temperature conversion. The BUSY bit is high whenever the TMP411/TMP411D device is converting a temperature reading.

8.6 Configuration Register

The Configuration Register sets the temperature range, controls shutdown mode, and determines how the

ALERT and THERM2 pins function. The Configuration Register is set by writing to pointer address 09h and by

reading from pointer address 03h.

The MASK bit (bit 7) enables or disables the ALERT pin output if AL or TH = 0. If AL or TH = 1, then the MASK

bit has no effect. If MASK is set to 0, the ALERT pin goes low when one of the temperature measurement

channels exceeds the high or low limits for the selected number of consecutive conversions. If the MASK bit is

set to 1, the TMP411/TMP411D retains the ALERT pin status, but the ALERT pin does not go low.

The shutdown (SD) bit (bit 6) enables or disables the temperature measurement circuitry. If SD = 0, the TMP411/

TMP411D converts continuously at the rate set in the conversion rate register. When SD is set to 1, the TMP411/

TMP411D immediately stops converting and enters shutdown mode. When SD is set to 0 again, the TMP411/

TMP411D resumes continuous conversions. A single conversion starts by writing to the One-Shot Register when

SD = 1.

The AL or TH bit (bit 5) controls if the ALERT pin functions in ALERT mode or THERM2 mode. If AL or TH =

0, the ALERT pin operates as an interrupt pin. In this mode, the ALERT pin goes low after the set number of

consecutive out-of-limit temperature measurements occur.

TMP411, TMP411D

SBOS383E – DECEMBER 2006 – REVISED JULY 2025

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