TMUX7436F datasheet(36/50 Pages) TI2

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VDD

VSS

GND

ESD

Protection

Logic &

Fault

Detection

40 k

SELx

Figure 8-1. Detailed Functional Diagram

8.3.2.5 Adjacent Channel Operation During Fault

When the logic pins are set to a channel under a fault, the overvoltage detection will trigger, the switch will open,

and the drain pin will operate as described in Section 8.3.2.4. During such an event, all other channels not under

a fault can continue to operate as normal. For example, if S1A voltage exceeds VDD, and the logic pins are set

to S1A, and the DR pin is set to logic low, then the drain output is pulled to VDD. Afterwards if the logic pins are

changed to set S1B, which is not in overvoltage or undervoltage, then the drain will disconnect from the pullup to

VDD and the S1B switch will be enabled and connected to the drain, operating as normal, although there is still

an overvoltage condition present on S1A. If the logic pins are switched back to S1A, then the S1B switch will be

disabled, the drain pin will be pulled up to VDD again, and the switch from S1A to drain will be disabled until the

overvoltage fault is removed.

8.3.2.6 ESD Protection

All pins on the TMUX7436F support HBM ESD protection level up to ±6 kV, which helps prevent the device from

being damaged by ESD events during the manufacturing process.

The drain pins (Dx) have internal ESD protection diodes to the supplies VDD and VSS; therefore the voltage at

the drain pins must not exceed the supply voltages to prevent excessive diode current. The source pins have

specialized ESD protection that allows the signal voltage to reach ±60 V regardless of supply voltage level.

Exceeding ±60 V on any source input may damage the ESD protection circuitry on the device and cause the

device to malfunction if the damage is excessive.

8.3.2.7 Latch-Up Immunity

Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition

is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains

even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic

damage due to excessive current levels. The latch-up condition typically requires a power cycle to eliminate the

low impedance path.

The TMUX7436F device is constructed on silicon on insulator (SOI) based process where an oxide layer is

added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic structures from

forming. The oxide layer is also known as an insulating trench and prevents triggering of latch up events due

to overvoltage or current injections. The latch-up immunity feature allows the TMUX7436F to be used in harsh

environments. For more information on latch-up immunity, refer to Using Latch Up Immune Multiplexers to Help

Improve System Reliability.

TMUX7436F

SCDS459A – OCTOBER 2022 – REVISED NOVEMBER 2022

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